1. Pyxis April Lewis Aaron Martin Steve Sherk

2. 2 Pyxis1600 General-purpose 16-bit RISC microprocessor 16 16-bit registers 16-bit address bus Up to 64KB of addressable memory

3. 3 Registers 16 registers 3 special purpose –$r0 – zero –$r14 – stack pointer –$r15 – return address 13 general purpose –$r1 - $r13 Status register (sr) –8 bits – carry (c), overflow (o), negative (n), zero (z), interrupt enable (i), less than (l), 2 bits unused Program counter (pc) Accumulator high (ah) and accumulator low (al) –Used for multiply and divide Interrupt Return Address (IRA) –Register to hold return address from interrupt

4. 4 Instruction Formats 16-bit instructions 7-bit opcode 1 bit to indicate information in next word rd is source and target rs is source Branch instructions use special format opcoderdrs Displacement / Immediate ext 0 015 3 4789 opcodebranch typeaddress 089121315 R-type B-type

5. 5 Instruction Set CategoryInstructionExample Opcode [15:9] Opcode [8]Meaning Arithmetic addadd, 00000010r3 = r3 + r4 add immediateaddi, #10000000011r3 = r3 + 100 subtractsub, 00000100r3 = r3 - r4 subtract immediatesubi, #20000000101r3 = r3 - 200 dividediv, 00001000 = r3 / r4 divide immediatedivi, #400001001 = r3 / 4 multiplymult, 00000110 = r3 * r4 multiply immediatemulti, #600000111 = r3 * 6 move from almal 1010000xr4 = (al) move from ahmah 1011111xr4 = (ah) Data Transfers load wordlw, 100( )00111111r3 = Memory[r4 + 100] store wordsw 200( ), 00100001Memory[r3 + 200] = r4 Logical andand, 00001000r3 = r3 & r4 andiandi, #400001001r3 = r3 & 4 oror, 00001010r3 = r3 | r4 oriori, #400001011r3 = r3 | 4 nornor, 00001100r3 = ~(r3 | r4) norinori, #400001101r3 = ~(r3 | 4) compcomp, 11111110set sr bits after compare shlshl, #1000001110r3 = r3 << 10 shrshr, #1000010000r3 = r3 >> 10

6. 6 Instruction Set Assembly to Machine Code Example add r3, r4; compr10, r4; beq#25; jmprr9; 0000001 0 0011 0100 1111111 1 1010 0100 1110000 x xxxx xxxx 0000 0000 0001 1001 010xxxx x 1001 0000 CategoryInstructionExample Opcode [15:9] Opcode [8]Meaning Conditional Branch beqbeq #1001110000xif sr[z] = 1, go to PC + 100 bnebne #1001110001xif sr[z] = 0, go to PC + 100 bltblt #1001110010xif sr[l] = 1, go to PC + 100 bgtbgt #1001110011xif (sr[l] = 0) & (sr[z] = 0), go to PC + 100 Unconditional Branch jmpjmp 2500100xxxx1go to 2500 jmpljmpl 2500011xxxxxr15 = PC + 2, go to 2500 jmpr 010xxxxxgo to r4 Other reti 001001xenables interrupts and reloads PC no operationnop0000000xstall for one clock cycle

7. 7 Addressing Modes Register direct Register indirect plus displacement –Use r0 for absolute addressing PC-relative Immediate

8. 8 Datapath

9. 9 Control Signals

10. 10 Control Signals Actions of n-bit Control Signals Signal NameEffect When DeassertedEffect When Asserted ALUSrcA00The first input to the ALU is the contents of the A register 01 The first input to the ALU is the contents of the Memory Data Register 10The first input to the ALU is the value of the PC 11None ALUSrcB00The second input to the ALU is the contents of the B register 01 The second input to the ALU is the contents of the Memory Data Register 10The second input to the ALU is the value 2 11 The second input to the ALU is the value of the Instruction Register [8:0] ALUOp000Add 001Subtract 010AND 011OR 100NOR 101Set on less than 110Multiply 111Divide

11. 11 State Transition Diagram Fetch IRWrite=1 RegWrite=0 PCWrite=0 Decode R-type (ext=0) 0 1 2 3 Write-back ALU to Reg Execute R-type (ext=1) 4 5 Calc EA or Immediate 9 6 8 Calc EA Memory Read Fetch Immediate IorD=0 MemRead=1 MemWrite=0 ALUOp=ADD ALUSrcA=2 ALUSrcB=2 PCSrc=0 PCWrite=1 RegWrite=0 ALUSrcA=0 ALUSrcB=0 ALUOp=OP IRWrite=0 RegWrite=0 PCWrite=0 RegWrite=1 MemtoReg=0 ALUOp=OFF IRWrite=0 PCWrite=0 IorD=0 MemRead=1 MemWrite=0 IRWrite=0 ALUOp=ADD ALUSrcA=2 ALUSrcB=2 PCSrc=0 PCWrite=1 RegWrite=0 IorD=1 MemRead=1 ALUOp=OFF RegWrite=0 IRWrite=0 PCWrite=0 RegWrite=1 MemtoReg=1 ALUOp=OFF IRWrite=0 PCWrite=0 Write-back Mem to Reg ALUSrcA=1 ALUSrcB=0 ALUOp=OP IRWrite=0 RegWrite=0 PCWrite=0 IorD=1 MemWrite=1 ALUOp=OFF RegWrite=0 IRWrite=0 PCWrite=0 7 Check Interrupt ALUSrcA=0 ALUSrcB=1 ALUOp=ADD IRWrite=0 RegWrite=0 PCWrite=0 Memory Write Arithmetic Instructions Write to Reg from ALU Load from Memory Write to Memory To State 0 15

12. 12 State Transition Diagram 10 11 12 13 ALUSrcA=0 ALUSrcB=0 ALUOp=ADD PCSrc=0 PCWrite=1 IRWrite=0 RegWrite=0 Jump to Reg Addr R-type Jump (ext=0) PCSrc=1 PCWrite=1 IorD=0 MemRead=1 MemWrite=0 ALUOp=OFF RegWrite=0 IRWrite=0 R-type Jump &Link Save Return Addr RegWrite=1 MemtoReg=1 ALUOp=OFF IRWrite=0 PCWrite=0 ALUSrcA=0 ALUSrcB=0 ALUOp=SUB IRWrite=0 RegWrite=0 PCWrite=0 Compare ALUSrcA=2 ALUSrcB=3 ALUOp=ADD PCCond=1 PCSrc=0 PCWrite=1 IRWrite=0 RegWrite=0 Update PC 14 R-type Jump (ext=1) Jump Fetch IRWrite=1 RegWrite=0 PCWrite=0 Decode 0 IorD=0 MemRead=1 MemWrite=0 ALUOp=ADD ALUSrcA=2 ALUSrcB=2 PCSrc=0 PCWrite=1 RegWrite=0 1 B-type Conditional Branch Jump to Register Address Jump to Register Address and Link Jump to Immediate and Link Jump to Immediate To State 15

13. 13 Interrupts Interrupts will be checked at the completion of each instruction An interrupt will trigger some extra states that send the processor to an Interrupt Service Routine (ISR), pre-programmed in code memory. These states will perform the following: –Save the processor’s state –Disable interrupts –Jump to the ISR The ‘RETI’ instruction will return the processor from the ISR

14. 14 Virtex XCV300 FPGA XCV300 FPGA - 322,970 logic gates - 8 KB on-chip RAM - Block SelectRAM - Fast arithmetic carry - Clock Speed 10MHZ - Multiple I/O standards (LVTTL, LVCOMS2)

15. 15 Input / Output Serial Interface UART Transmitter and Receiver Macros UART_TX 8-bit Serial 16 Byte FIFO BUFFER 8-bit Serial 16 Byte FIFO BUFFER UART_RX These macros are fully compatible with standard UART communications protocols such as to a PC, providing level shifting components are employed to generate RS232 signaling. The buffers will be interrupt driven.

16. 16 Memory Timing Diagrams 32KB FLASH (AT29C256-70PC) Total access time is 70ns (tACC) 70ns

17. 17 Memory Timing Diagrams 32KB SRAM (K6x0808C1D-DF70) Total access time is 70ns (tAA)

18. 18 32KBx8 off-chip SRAM 32KBx8 off-chip FLASH

19. 19 Parts List

20. 20 Roles and Responsibilities Aaron –Logic design –Verilog programming –Hardware implementation April –Logic design –Verilog programming –Assembler Steve –Logic design –Verilog programming –Hardware implementation All –Test programs –Integration and Test –Documentation

21. 21 Schedule

22. Questions