1. Parking Pal Presentation #6 Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Project Manager: Kartik Murthy October 10, 2007 Schematic Review! Your digital parking meter of the future!

2. Status Project Chosen Options explored and eliminated Wrote Java Implementation Specification defined Verilog obtained/modified Test Benches Schematic Design  Layout*  Simulations

3. Encryption Block Parts in Encryption Block:  2x 16 bits register  16 bits Mux  32 bits Mux  FSM(encryption)  Encryptor (Small Encryption Block)

4. FSM Encryption

5. FSM Encryption (Wave)

6. Encryption Cell

7. Encryption Cell (Wave)

8. Full Encryption Block

9. Full Encryption Wave

10. Tickets Block This block is responsible for determining how much time a car has left to park, and whether or not a car should be ticketed. Major Components: –11-Bit Adder, 11-Bit Subtractor, 11-Bit Comparator.

12. SRAM  Included in the following slides are simulation results for an SRAM cell and mult-adder block.  Design decision made:  Not pre-charging for reading because it makes it faster not more power efficient

13. SRAM Cell

14. SRAM Cell Wave

15. SRAM FSM

16. SRAM FSM WAVE

17. Overall SRAM

18. Full SRAM Wave

19. 7-Segment Display  Included in the following slides are simulation results for a 7-Segment Display block

20. Binary to BCD (4 bits)

21. Parallel to Serial

22. 7-Seg Display Cell

23. Full 7-Seg Display Block

24. Full 7-Seg Display(Wave)

25. Overall Design Schematic

26. Layout*

27. Things to Do Power FSM Layout More Layout