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Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 111 Lecture 11 Major Combinational Automatic Test-Pattern Generation Algorithms n Definitions n D-Algorithm.

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Presentation on theme: "Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 111 Lecture 11 Major Combinational Automatic Test-Pattern Generation Algorithms n Definitions n D-Algorithm."— Presentation transcript:

1 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 111 Lecture 11 Major Combinational Automatic Test-Pattern Generation Algorithms n Definitions n D-Algorithm (Roth) -- 1966  D-cubes  Bridging faults  Logic gate function change faults n PODEM (Goel) -- 1981  X-Path-Check  Backtracing n Summary

2 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 112 Forward Implication n Results in logic gate inputs that are significantly labeled so that output is uniquely determined n AND gate forward implication table:

3 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 113 Backward Implication n Unique determination of all gate inputs when the gate output and some of the inputs are given

4 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 114 Implication Stack n Push-down stack. Records:  Each signal set in circuit by ATPG  Whether alternate signal value already tried  Portion of binary search tree already searched

5 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 115 Implication Stack after Backtrack 0 1 0 0 0 0 0 1 1 1 1 E F BB F F 1 Unexplored Present Assignment Searched and Infeasible

6 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 116 Objectives and Backtracing of ATPG Algorithm n Objective – desired signal value goal for ATPG  Guides it away from infeasible/hard solutions n Backtrace – Determines which primary input and value to set to achieve objective  Use testability measures

7 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 117 Branch-and-Bound Search n Efficiently searches binary search tree n Branching – At each tree level, selects which input variable to set to what value n Bounding – Avoids exploring large tree portions by artificially restricting search decision choices  Complete exploration is impractical  Uses heuristics

8 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 118 D-Algorithm -- Roth IBM (1966) n Fundamental concepts invented:  First complete ATPG algorithm  D-Cube  D-Calculus  Implications – forward and backward  Implication stack  Backtrack  Test Search Space

9 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 119 Singular Cover Example n Minimal set of logic signal assignments to show essential prime implicants of Karnaugh map Gate AND 1 2 3 Inputs A 0 X 1 BX01BX01 Output d 0 1 Gate NOR 1 2 3 Inputs d 1 X 0 eX10eX10 Output F 0 1

10 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1110 D-Cube n Collapsed truth table entry to characterize logic n Use Roth’s 5-valued algebra n Can change all D’s to D’s and D’s to D’s (do both) n AND gate: Rows 1 & 3 Reverse inputs And two cubes Interchange D and D AD1DD1DAD1DD1D B1DDDD1B1DDDD1 dDDDDDDdDDDDDD

11 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1111 D-Cube Operation of D-Intersection  – undefined (same as  )  or – requires inversion of D and D n D-intersection: 0 0 = 0 X = X 0 = 0 1 1 = 1 X = X 1 = 1 X X = X n D-containment – Cube a contains Cube b if b is a subset of a 01XDD01XDD 000000 111111 X01XDDX01XDD D  D  D  D         

12 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1112 Primitive D-Cube of Failure n Models circuit faults:  Stuck-at-0  Stuck-at-1  Bridging fault (short circuit)  Arbitrary change in logic function n AND Output sa0: “1 1 D” n AND Output sa1: “0 X D ” “X 0 D ” n Wire sa0: “D” n Propagation D-cube – models conditions under which fault effect propagates through gate

13 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1113 Implication Procedure 1. Model fault with appropriate primitive D-cube of failure (PDF) 2. Select propagation D-cubes to propagate fault effect to a circuit output (D-drive procedure) 3. Select singular cover cubes to justify internal circuit signals (Consistency procedure) n Put signal assignments in test cube n Regrettably, cubes are selected very arbitrarily by D-ALG

14 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1114 Bridging Fault Circuit

15 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1115 Construction of Primitive D-Cubes of Failure 1. Make cube set  1 when good machine output is 1 and set  0 when good machine output is 0 2. Make cube set  1 when failing machine output is 1 and  0 when it is 0 3. Change  1 outputs to 0 and D-intersect each cube with every  0. If intersection works, change output of cube to D 4. Change  0 outputs to 1 and D-intersect each cube with every  1. If intersection works, change output of cube to D

16 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1116 Bridging Fault D-Cubes of Failure Cube-set  0  1  0  1 a0X1X0X1a0X1X0X1 bX0X101XbX0X101X a* 0 X 1 X 0 1 b* X 0 X 1 0 1 Cube-set PDFs for Bridging fault b01b01 a* 1 D b* D 1 a10a10

17 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1117 Gate Function Change D-Cube of Failure Cube-set  0  1  0  1 a0X101Xa0X101X bX010X1bX010X1 c001011c001011 Cube-set PDFs for AND changing to OR a01a01 b10b10 cDDcDD

18 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1118 D-Algorithm – Top Level 1.Number all circuit lines in increasing level order from PIs to POs; 2.Select a primitive D-cube of the fault to be the test cube;  Put logic outputs with inputs labeled as D (D) onto the D-frontier; 3. D-drive (); 4. Consistency (); 5.return ();

19 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1119 D-Algorithm – D-drive while (untried fault effects on D-frontier) select next untried D-frontier gate for propagation; while (untried fault effect fanouts exist) select next untried fault effect fanout; generate next untried propagation D-cube; D-intersect selected cube with test cube; if (intersection fails or is undefined) continue; if (all propagation D-cubes tried & failed) break; if (intersection succeeded) add propagation D-cube to test cube -- recreate D-frontier; Find all forward & backward implications of assignment; save D-frontier, algorithm state, test cube, fanouts, fault; break; else if (intersection fails & D and D in test cube) Backtrack (); else if (intersection fails) break; if (all fault effects unpropagatable) Backtrack ();

20 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1120 D-Algorithm -- Consistency g = coordinates of test cube with 1’s & 0’s; if (g is only PIs) fault testable & stop; for (each unjustified signal in g) Select highest # unjustified signal z in g, not a PI; if (inputs to gate z are both D and D) break; while (untried singular covers of gate z) select next untried singular cover; if (no more singular covers) If (no more stack choices) fault untestable & stop; else if (untried alternatives in Consistency) pop implication stack -- try alternate assignment; else Backtrack (); D-drive (); If (singular cover D-intersects with z) delete z from g, add inputs to singular cover to g, find all forward and backward implications of new assignment, and break; If (intersection fails) mark singular cover as failed;

21 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1121 Backtrack if (PO exists with fault effect) Consistency (); else pop prior implication stack setting to try alternate assignment; if (no untried choices in implication stack) fault untestable & stop; else return;

22 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1122 Circuit Example 7.1 and Truth Table Inputs A 0 1 B00110011B00110011 C01010101C01010101 Output F 0 1 0

23 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1123 Singular Cover & D-Cubes n Singular cover – Used for justifying lines n Propagation D-cubes – Conditions under which difference between good/failing machines propagates A10D1DA10D1D B10101DDD1DB10101DDD1D C101DDC101DD d10010DDDD0Dd10010DDDD0D e01110DDD0DDe01110DDD0DD F001DDDF001DDD

24 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1124 Steps for Fault d sa0 Step 1 2 3 A1A1 B11B11 C1C1 dDDdDD e00e00 FDFD Cube type PDF of AND gate Prop. D-cube for NOR Sing. Cover of NAND

25 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1125 Example 7.2 Fault A sa0 n Step 1 – D-Drive – Set A = 1 D 1 D

26 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1126 Step 2 -- Example 7.2 D 1 0 D n Step 2 – D-Drive – Set f = 0 D

27 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1127 Step 3 -- Example 7.2 D 1 0 D n Step 3 – D-Drive – Set k = 1 D 1 D

28 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1128 Step 4 -- Example 7.2 D 1 0 D n Step 4 – Consistency – Set g = 1 D 1 D 1

29 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1129 Step 5 -- Example 7.2 D 1 0 D n Step 5 – Consistency – f = 0 Already set D 1 D 1

30 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1130 Step 6 -- Example 7.2 D 1 0 D n Step 6 – Consistency – Set c = 0, Set e = 0 D 1 D 1 0 0

31 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1131 D-Chain Dies -- Example 7.2 D 1 0 X D n Step 7 – Consistency – Set B = 0 n Fault detected at PO, although D-Chain dies D 1 D 1 0 0 0 n Test cube: A, B, C, D, e, f, g, h, k, L

32 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1132 Example 7.3 – Fault s sa1 n Primitive D-cube of Failure 1 D sa1

33 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1133 Example 7.3 – Step 2 s sa1 n Propagation D-cube for v 1 D 0 sa1 D 1 D

34 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1134 Example 7.3 – Step 2 s sa1 n Forward & Backward Implications 1 D sa1 0 D D 1 1 0 1 1

35 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1135 Example 7.3 – Step 3 s sa1 n Propagation D-cube for Z – test found! 1 D sa1 0 D D 1 1 0 1 1 1 D

36 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1136 Example 7.3 – Fault u sa1 n Primitive D-cube of Failure 1 D 0 sa1

37 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1137 Example 7.3 – Step 2 u sa1 n Propagation D-cube for v 1 D 0 sa1 D 0

38 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1138 Example 7.3 – Step 2 u sa1 n Forward and backward implications 1 D 0 sa1 D 0 0 1 0 1 0

39 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1139 Inconsistent n d = 0 and m = 1 cannot justify r = 1 (equivalence)  Backtrack  Remove B = 0 assignment

40 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1140 Example 7.3 – Backtrack n Need alternate propagation D-cube for v 1 sa1 D 0

41 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1141 Example 7.3 – Step 3 u sa1 n Propagation D-cube for v 1 sa1 D 0 1 D

42 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1142 Example 7.3 – Step 4 u sa1 n Propagation D-cube for Z D 1 sa1 D 0 1 D 1 1

43 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1143 Example 7.3 – Step 4 u sa1 n Propagation D-cube for Z and implications D 1 sa1 D 0 1 D 1 1 0 0 0 1 1

44 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1144 PODEM -- Goel IBM (1981) n New concepts introduced:  Expand binary decision tree only around primary inputs  Use X-PATH-CHECK to test whether D-frontier still there  Objectives -- bring ATPG closer to propagating D (D) to PO  Backtracing

45 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1145 Motivation n IBM introduced semiconductor DRAM memory into its mainframes – late 1970’s n Memory had error correction and translation circuits – improved reliability  D-ALG unable to test these circuits n Search too undirected n Large XOR-gate trees n Must set all external inputs to define output  Needed a better ATPG tool

46 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1146 PODEM High-Level Flow 1. Assign binary value to unassigned PI 2. Determine implications of all PIs 3. Test Generated? If so, done. 4. Test possible with more assigned PIs? If maybe, go to Step 1 5. Is there untried combination of values on assigned PIs? If not, exit: untestable fault 6. Set untried combination of values on assigned PIs using objectives and backtrace. Then, go to Step 2

47 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1147 n Select path s – Y for fault propagation sa1 Example 7.3 Again

48 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1148 n Initial objective: Set r to 1 to sensitize fault 1 sa1 Example 7.3 -- Step 2 s sa1

49 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1149 Example 7.3 -- Step 3 s sa1 n Backtrace from r 1 sa1

50 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1150 Example 7.3 -- Step 4 s sa1 n Set A = 0 in implication stack 1 0 sa1

51 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1151 Example 7.3 -- Step 5 s sa1 n Forward implications: d = 0, X = 1 1 sa1 0 0 1

52 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1152 Example 7.3 -- Step 6 s sa1 n Initial objective: set r to 1 1 sa1 0 0 1

53 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1153 Example 7.3 -- Step 7 s sa1 n Backtrace from r again 1 sa1 0 0 1

54 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1154 Example 7.3 -- Step 8 s sa1 n Set B to 1. Implications in stack: A = 0, B = 1 1 sa1 0 0 1 1

55 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1155 D Example 7.3 -- Step 9 s sa1 n Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1 1 sa1 1 0 1 1 D D 1 0 1 0 1

56 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1156 Backtrack -- Step 10 s sa1 n X-PATH-CHECK shows paths s – Y and s – u – v – Z blocked (D-frontier disappeared) 1 sa1 0 0 1

57 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1157 Step 11 -- s sa1 n Set B = 0 (alternate assignment) 1 sa1 0 0

58 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1158 Backtrack -- s sa1 1 sa1 0 0 1 0 1 0 1 0 1 0 1 n Forward implications: d = 0, X = 1, m = 1, r = 0, s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.

59 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1159 Step 13 -- s sa1 n Set A = 1 (alternate assignment) 1 sa1 1

60 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1160 Step 14 -- s sa1 n Backtrace from r again 1 sa1 1

61 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1161 Step 15 -- s sa1 n Set B = 0. Implications in stack: A = 1, B = 0 1 sa1 1 0

62 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1162 Backtrack -- s sa1 n Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack sa1 1 0 0 0 1 1 1 1 1 0 0 1

63 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1163 Step 17 -- s sa1 n Set B = 1 (alternate assignment) 1 sa1 1 1

64 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1164 Fault Tested -- Step 18 s sa1 n Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D 1 sa1 1 1 1 1 0 D 0 D D X D

65 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1165 Backtrace (s, v s ) Pseudo-Code v = v s ; while (s is a gate output) if (s is NAND or INVERTER or NOR) v = v; if (objective requires setting all inputs) select unassigned input a of s with hardest controllability to value v; else select unassigned input a of s with easiest controllability to value v; s = a; return (s, v) /* Gate and value to be assigned */;

66 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1166 Objective Selection Code if (gate g is unassigned) return (g, v); select a gate P from the D-frontier; select an unassigned input l of P; if (gate g has controlling value) c = controlling input value of g; else if (0 value easier to get at input of XOR/EQUIV gate) c = 1; else c = 0; return (l, c );

67 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1167 PODEM Algorithm while (no fault effect at POs) if (xpathcheck (D-frontier)) (l, v l ) = Objective (fault, v fault ); (pi, v pi ) = Backtrace (l, v l ); Imply (pi, v pi ); if (PODEM (fault, v fault ) == SUCCESS) return (SUCCESS); (pi, v pi ) = Backtrack (); Imply (pi, v pi ); if (PODEM (fault, v fault ) == SUCCESS) return (SUCCESS); Imply (pi, “X”); return (FAILURE); else if (implication stack exhausted) return (FAILURE); else Backtrack (); return (SUCCESS);

68 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 1168 Summary n D-ALG – First complete ATPG algorithm  D-Cube  D-Calculus  Implications – forward and backward  Implication stack  Backup n PODEM  Expand decision tree only around PIs  Use X-PATH-CHECK to see if D-frontier exists  Objectives -- bring ATPG closer to getting D (D) to PO  Backtracing

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