1. Viterbi Decoder: Presentation #7 M1 Overall Project Objective: Design a high speed Viterbi Decoder Stage 7: 1st Mar. 2004 Component layout (corrected) Design Manager: Yaping Zhan Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun

2. Status 18-525, Integrated Circuits Design Project Design Proposal (Done) Architecture Proposal (Done) Gate level Design(Done) Component Layout (DRC & LVS): (Done) Major Blocks Layout: (Almost) BCU: 100% Trace Back: 100% ACS/ML Search: 80% To be done: Chip Layout Spice Simulation of Entire Chip

3. 18-525, Integrated Circuits Design Project Old Floorplan 18-525, Integrated Circuits Design Project M4 M2 M3

4. New Floorplan 18-525, Integrated Circuits Design Project

5. Dimensions 18-525, Integrated Circuits Design Project Old: 318 x 285 sq. um ~22,500 transistors Density – 0.248 New: 319 x 219 sq. um ~21,000 transistors Density – 0.3005

6. 3 bits stage in MLSearch(Old) 18-525, Integrated Circuits Design Project

7. 3 bits stage in MLSearch(New)

8. Old ACS Unit (Schematic) 18-525, Integrated Circuits Design Project

9. New ACS Unit (Schematic) 18-525, Integrated Circuits Design Project

10. Top Level Schematic (Old) 18-525, Integrated Circuits Design Project

11. Top Level Schematic (New)

12. Simulations still match!! 18-525, Integrated Circuits Design Project

13. Trace Back 18-525, Integrated Circuits Design Project

14. BCU Cell

15. BCU Unit (Layout) 18-525, Integrated Circuits Design Project

16. New Comparator Layout

17. 18-525, Integrated Circuits Design Project Comparator 8b (50 fF) Propagation Delay Worst Case: 2.23 ns

18. New comparator Propagation Delay Worst Case = 812 ps.

19. New comparator falling Worst Case = 805 ps.

20. 18-525, Integrated Circuits Design Project Questions?