1. 1 8 Bit Gray Code Converter Rasha Shaba Hala Shaba Kai Homidi Advisor: David Parent DATE 12/06/04

2. 2 Agenda Abstract Introduction –Why –Simple Theory –Back Ground information Project (Experimental) Details Verifications of Results Lessons Learned Summary

3. 3 Abstract We designed an 8-bit gray code converter according to the following specifications.  Frequency: 200 MHz.  Power: <25mW  Area: <800  mx800  m

4. 4 Introduction We chose a gray code converter for our project because  It is applied in a broad range of applications  It incorporates all principles taught in EE-166 The basic theory of our project is to convert a series of binary numbers to gray code numbers with the use of XOR gates

5. 5 The Gray Code Natural Binary Gray Code 0 00000000 1 00010001 2 00100011 3 00110010

6. 6 Project Details The Gray Code Converter consists of the following:  NAND gates  XOR gates  D Flip Flops

7. 7 NAND Gate

8. 8 NANDNAND

9. 9 XOR Gate

10. 10 XOR

11. 11 XOR XORXOR

12. 12 DFF

13. 13 DFF

14. 14 Longest Path Calculations Note: All widths are in microns and capacitances in fF

15. 15 Gray Code Converter Schematic

16. 16 Gray Code Converter Layout

17. 17 Verification (LVS)

18. 18 Input DataOutput Data

19. 19 Verification of Specifications  Frequency: 200 MHz  Power: 5mW  Area: 178  mx555  m  Logic: Functional

20. 20 Lessons Learned Advice to EE-166 students:  Start early  Consult with Professor Parent in office hours  Pay attention to lecture  Think of the project as a learning experience Advice to EE-166 professors:  Narrow down class notes to more useful examples

21. 21 Summary The gray code converter project was worthwhile because it firmly illustrated the principles taught in EE-166 course The main results of the project are the following  Timing specifications were met  The basic principles of design and layout of CMOS technology were learned Gray code converters will continue to be a main components in may systems to come

22. 22 Acknowledgements Thanks to Hala, Kai, & Rasha for putting up with us. Thanks to Cadence Design Systems for the VLSI lab Thanks to Synopsys for Software donation Professor David Parent