1. Power Aware Solutions for NoC Architecture Yaniv Ben-Itzhak Noc Seminar Winter 08

2. Power Aware Various Solutions SoC Mapping blocks. Routing. Scheduling. CMP (MPSoC) Threads Allocation. Routing. Scheduling.

3. Power Aware Various Solutions SoC Mapping blocks. Routing. Scheduling. CMP (MPSoC) Threads Allocation. Routing. Scheduling.

4. SoC Radu Marculescu & Jingcao Hu: Exploiting the Routing Flexibility for Energy Performance Aware Mapping of Regular NoC Architectures (2003) Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time (2004) Energy-and Performance-Aware Mapping for Regular NoC Architectures (2005) Communication and Task Scheduling of Application-Specific Networks-on- Chip (2005)

5. Problem Formulation How to map each IP to which tile ? Total communication energy consumption is minimized

6. Communication Energy Model Energy consumed by the switch Energy consumed on the links Energy consumed by the buffer Energy consumed by the internal wires negligible

7. Communication Energy Model Energy consumed by the switch Energy consumed on the links

8. Communication Energy Model Energy consumed by the switch Energy consumed on the links Calculated independently of the underlying traffic model. Determined by the Manhattan distance between them.

9. Solution Application Characterization Graph (APCG) G = G(C,A) : c i represents one selected IP. a i, j characterizes the communication from c i to c j. v(a i, j ): communication volume (bits) from c i to c j. b(a i, j ): arc minimum bandwidth requirement from vertex c i to c j,

10. Solution Architecture Characterization Graph (ARCG) G =G(T,R): t i represents one tile in the architecture. r i, j represents the routing from t i to t j: P i, j : a set of candidate minimal paths from tile t i to tile t j. e(r i, j ):

11. Solution Find mapping function map() from APCG to ARCG and a deadlock-free, minimal routing function, which: communication volume (bits) from c i to c j

12. Solution The search space of the problem increases factorially with the system size. For System with 4X4 tiles, there are 16! Possible mappings !!

13. Solution Branch-and-Bound Algorithm

14. Power Aware Various Solutions SoC Mapping blocks. Routing. Scheduling. CMP Threads Allocation. Routing. Scheduling.

15. 1 CMP (MPSoC( Threads Allocation 23 12123412 Nero PhotoShop WinRar Quake 4 Threads Allocation

16. 123 12123412 Nero PhotoShop WinRar Quake 4 Off CMP (MPSoC( Threads Allocation

18. CMP (MPSoC( Basic Processor Model Cache Miss T(p) Idle t(p)... 12 p Cache Miss …

19. CMP (MPSoC( Basic Processor Model Power = Power processors + Power NoC

20. CMP (MPSoC( Basic Processor Model Power = Power processors + Power NoC Power NoC calculated by bit energy model Depends on the Architecture (Cache in the Middle,Tiled CMP, Message Passing)

21. CMP (MPSoC( Basic Processor Model Threads Total Average Performance (All processors)

22. CMP (MPSoC( Power = Power processors + Power NoC P NoC calculated by bit energy model

23. CMP (MPSoC( Avg. Performance Threads Performance Average

24. CMP (MPSoC( Threads Allocation with constraints of: Asymmetry. Shared Memory –  Cache in the Middle  Tiled CMP Architecture. Message Passing. Threads Allocation with: Processors On/Off. DVS - Dynamic Voltage Scaling. DFS - Dynamic Frequency Scaling.

25. Questions ? Thank You !