1. Microprocessors Introduction to RISC Mar 19th, 2002

2. RISC Reduced Instruction Set Computing Reduced Instruction Set Computing (Reduced Instruction) Set (Reduced Instruction) Set Not Reduced (Instruction Set) Not Reduced (Instruction Set) Number of instructions may be large Number of instructions may be large But each instruction is simple and uniform But each instruction is simple and uniform

3. Instruction Formats Fixed length instructions Fixed length instructions 32-bits for all common RISC instructions 32-bits for all common RISC instructions Small number of uniform formats Small number of uniform formats E.g. Opcode always in first 8 bits E.g. Opcode always in first 8 bits Large number of uniform registers Large number of uniform registers Typical 32 32-bit or 64-bit integer registers Typical 32 32-bit or 64-bit integer registers 32 64-bit floating-point registers 32 64-bit floating-point registers

4. More on Instruction Formats Register-register format usually 3-address Register-register format usually 3-address Rdest  Rsrc1 (Op) Rsrc2 Rdest  Rsrc1 (Op) Rsrc2 This allows variables to be assigned to regs This allows variables to be assigned to regs Register zero often wired to zero Register zero often wired to zero Now for example OR can be a MOVE Now for example OR can be a MOVE XOR can be a NOT XOR can be a NOT

5. Memory Access Usually only Load, or Store Usually only Load, or Store No other instructions reference memory No other instructions reference memory Limited addressing modes Limited addressing modes Register indirect Register indirect Register + register Register + register Register + offset Register + offset

6. Jump Instructions Unconditional jump Unconditional jump May have special format to allow wide range May have special format to allow wide range Conditional jumps Conditional jumps Usually use a signed offset as on x86 Usually use a signed offset as on x86 Large range not needed Large range not needed Most usually test a register Most usually test a register Rather than dedicated flag registers Rather than dedicated flag registers Addressing is direct, or via register Addressing is direct, or via register

7. Call Instructions Call often has special format Call often has special format To give a wide range To give a wide range Sets return point in a register Sets return point in a register This may be one place that a register is dedicated This may be one place that a register is dedicated Why? Because we are really cramped for space in a call instruction Why? Because we are really cramped for space in a call instruction Call must operate between units Call must operate between units But a jump only needs to operate in a unit But a jump only needs to operate in a unit

8. Floating-Point Usually uses a separate set of registers Usually uses a separate set of registers Provides standard arithmetic operations Provides standard arithmetic operations Nearly always uses IEEE fpt formats Nearly always uses IEEE fpt formats Typically very aggressive implementations Typically very aggressive implementations To get best possible speed To get best possible speed Heavily pipelined Heavily pipelined

9. Memory Addressing Simple linear addressing Simple linear addressing No segmentation stuff No segmentation stuff Virtual memory using paging Virtual memory using paging Maybe software TLB reload Maybe software TLB reload Or hardware TLB reload Or hardware TLB reload Provides memory protection Provides memory protection

10. Instruction Parallelism May be completely invisible May be completely invisible But maybe visible But maybe visible Load delay on MIPS Load delay on MIPS If instruction loads a register If instruction loads a register Then register may not be used in next instruction Then register may not be used in next instruction Originally idea on MIPS was no interlocks Originally idea on MIPS was no interlocks An interlock here means waiting for a result An interlock here means waiting for a result But now with slow memory, must interlock But now with slow memory, must interlock

11. Jump Delay Slots Suppose you have Suppose you have ADD SUB JMP XOR ADD SUB JMP XOR Then XOR will happen *before* the JMP Then XOR will happen *before* the JMP Not all machines have jump delays Not all machines have jump delays Modern machines have more sophisticated scheduling using multiple pipelines Modern machines have more sophisticated scheduling using multiple pipelines

12. Kinds of Instructions Early RISC machines did have very limited instruction sets Early RISC machines did have very limited instruction sets For example, SPARC had no multiply or divide For example, SPARC had no multiply or divide Just a multiply step that did one step Just a multiply step that did one step Takes 32 such instructions to do multiply Takes 32 such instructions to do multiply But modern microprocessors change this But modern microprocessors change this Complex instructions taking many cycles Complex instructions taking many cycles Use special pipelines Use special pipelines With interlocks With interlocks

13. Protection Typically two modes Typically two modes User mode User mode System mode System mode Limited differences between them Limited differences between them Manipulation of memory mapping Manipulation of memory mapping I/O access I/O access Some kind of trap instruction to switch Some kind of trap instruction to switch

14. Interrupts and Traps Act as specialized calls Act as specialized calls To sets of OS routines To sets of OS routines Switch automatically into system mode Switch automatically into system mode But are otherwise like any other calls But are otherwise like any other calls

15. Fancy Stuff Register Windows Register Windows Notably on SPARC Notably on SPARC Allow automatic saving and restoring of registers on a call or return Allow automatic saving and restoring of registers on a call or return By moving a window within a much larger bank of registers By moving a window within a much larger bank of registers For example, may have 256 registers, but only 32 contiguous registers are visible. For example, may have 256 registers, but only 32 contiguous registers are visible.

16. Fancy Stuff Most other fancy stuff has to do with implementation that is *not* visible Most other fancy stuff has to do with implementation that is *not* visible Multiple pipelines Multiple pipelines Out of order execution Out of order execution Speculative execution Speculative execution These same tecniques are used in implementing CISC chips, so are not really RISC specific from an architecture view These same tecniques are used in implementing CISC chips, so are not really RISC specific from an architecture view

17. Next Lecture: MIPS MIPS MIPS The simplest RISC chip The simplest RISC chip One of the very early chips One of the very early chips Still used widely Still used widely SGI work stations SGI work stations Video games Video games Set top boxes Set top boxes