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MAPS for Particles Physics Christine Hu-Guo (IPHC) PHASE1 – STAR IPHC.

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Presentation on theme: "MAPS for Particles Physics Christine Hu-Guo (IPHC) PHASE1 – STAR IPHC."— Presentation transcript:

1 MAPS for Particles Physics Christine Hu-Guo (IPHC) PHASE1 – STAR IPHC

2 IPHC christine.hu@ires.in2p3.fr 2 October 2010 USTC Trends for Pixel Sensor Development CCD (Charge Coupled Device) Hybrid Pixel Detector  Future subatomic physics experiments need detectors  beyond the state of the art  MAPS provide an attractive trade-off between granularity, material budget, readout speed, radiation tolerance and power dissipation Power consumption Limited for all experiments 3DIT High resistivity EPI  2D & 3D MAPS MAPS Development Trend 3T pixel Analogue RO MAPS Digital RO MAPS

3 IPHC christine.hu@ires.in2p3.fr 3 October 2010 USTC Development of MAPS for Charged Particle Tracking In 1999, the IPHC CMOS sensor group proposed the first CMOS pixel sensor (MAPS) for future vertex detectors (ILC)  Numerous other applications of MAPS have emerged since then  ~10-15 HEP groups in the USA & Europe are presently active in MAPS R&D Original aspect: integrated sensitive volume (EPI layer) and front-end readout electronics on the same substrate  Charge created in EPI, excess carriers propagate thermally, collected by N WELL /P EPI, with help of reflection on boundaries with P-well and substrate (high doping) Q = 80 e - h / µm  signal < 1000 e -  Compact, flexible  EPI layer ~10–15 µm thick thinning to ~30–40 µm permitted  Standard fabrication technology Cheap, fast turn-around  Room temperature operation  Attractive balance between granularity, material budget, radiation tolerance, read out speed and power dissipation  BUT Very thin sensitive volume  impact on signal magnitude (mV!) Sensitive volume almost un-depleted  impact on radiation tolerance & speed Commercial fabrication (parameters)  impact on sensing performances & radiation tolerance N WELL used for charge collection  restricted use of PMOS transistors R.T.

4 IPHC christine.hu@ires.in2p3.fr 4 October 2010 USTC Achieved Performances with Analogue Readout MAPS provide excellent tracking performances  Detection efficiency ~100% ENC ~10-15 e - S/N > 20-30 (MPV) at room temperature  Single point resolution ~ µm, a function of pixel pitch ~ 1 µm (10 µm pitch), ~ 3 µm (40 µm pitch) MAPS: Final chips:  MIMOTEL (2006): ~66 mm², 65k pixels, 30 µm pitch EUDET Beam Telescope (BT) demonstrator  MIMOSA18 (2006): ~37 mm², 262k pixels, 10 µm pitch High resolution EUDET BT demonstrator  MIMOSTAR (2006): ~2 cm², 204k pixels, 30 µm pitch Test sensor for STAR Vx detector upgrade  LUSIPHER (2007): ~40 mm², 320k pixels, 10 µm pitch Electron-Bombarded CMOS for photon and radiation imaging detectors MIMOSTAR Chip dimension: ~2 cm² MIMOTEL M18 LUSIPHER

5 IPHC christine.hu@ires.in2p3.fr 5 October 2010 USTC Radiation tolerance (preliminary) Ionising radiation tolerance:  O(1 M Rad) (MIMOSA15, test cond. 5 GeV e -, T = -20°C, t int ~180 µs)  t int << 1 ms, crucial at room temperature Non ionising radiation tolerance: depends on pixel pitch:  20 µm pitch: 2x10 12 n eq /cm 2, (Mimosa15, tested on DESY e - beams, T = - 20°C, t int ~700 μs)  5.8·10 12 n eq /cm² values derived with standard and with soft cuts  10 µm pitch: 10 13 n eq /cm 2, (MIMOSA18, tested at CERN-SPS, T = - 20°C, t int ~ 3 ms)  parasitic 1–2 kGy gas  N ↑  Further studies needed : Tolerance vs diode size, Readout speed, Digital output,..., Annealing ?? Integ. DoseNoiseS/N (MPV)Detection Efficiency 0 9.0 ± 1.127.8 ± 0.5100 % 1 Mrad 10.7 ± 0.919.5 ± 0.299.96 % ± 0.04 % Fluence (10 12 n eq /cm²) 00.472.15.8 (5/2)5.8 (4/2) S/N (MPV) 27.8 ± 0.521.8 ± 0.514.7 ± 0.38.7 ± 2.7.5 ± 2. Det. Efficiency (%) 100.99.9 ± 0.199.3 ± 0.277. ± 2.84. ± 2. Fluence (10 12 n eq /cm²)0610 Q cluster (e - ) 1026680560 S/N (MPV) 28.5 ± 0.220.4 ± 0.214.7 ± 0.2 Det. Efficiency (%) 99.93 ± 0.0399.85 ± 0.0599.5 ± 0.1

6 IPHC christine.hu@ires.in2p3.fr 6 October 2010 USTC System integration Industrial thinning (via STAR collaboration at LBNL)  ~50 µm, expected to ~30-40 µm Ex. MIMOSA18 (5.5×5.5 mm² thinned to 50 μm) Development of ladder equipped with MIMOSA chips (coll. with LBNL)  STAR ladder (~< 0.3 % X 0 )  ILC (<0.2 % X 0 ) Edgeless dicing / stitching  alleviate material budget of flex cable Now 0.37 % Xo

7 IPHC christine.hu@ires.in2p3.fr 7 October 2010 USTC Analogue Readout Sensors  Digital Readout Sensors Analogue readout sensors : excellent performance BUT: moderate readout speed for larger sensors with smaller pitch! For many applications: high granularity and fast readout required simultaneously  Integrating signal processing: ADC, Data sparsification, …  Digital Readout Sensors  R&D on high readout speed, low noise, low power dissipation, highly integrated signal processing architecture with radiation tolerance

8 IPHC christine.hu@ires.in2p3.fr 8 October 2010 USTC Development of CMOS Pixel Sensors for Charged Particle Tracking Design according to 3 issues:  Increasing S/N at pixel-level  A to D Conversion at column-level  Zero suppression at chip edge level Power v.s. speed:  Power  Readout in a rolling shutter mode Speed  1 row pixels are read out // MIMOSA26 is a reticule size MAPS with binary output, 10 k images / s  Pixel array: 1152 x 576, 18.4 µm pitch  Hit density: ~ 10 6 particles/cm²/s  Architecture: Pixel (Amp+CDS) array organised in // columns r.o. in the rolling shutter mode 1152 ADC, a 1-bit ADC (discriminator) / column Integrated zero suppression logic Remote and programmable 21.5 mm 13.7 mm MIMOSA26 Active area: ~10.6 x 21.2 mm2 Pixel Array Rolling shutter mode ADC Zero suppression

9 IPHC christine.hu@ires.in2p3.fr 9 October 2010 USTC MIMOSA26: 1st MAPS with Integrated Ø Pixel array: 576 x 1152, pitch: 18.4 µm Active area: ~10.6 x 21.2 mm 2 In each pixel:  Amplification  CDS (Correlated Double Sampling) 1152 column-level discriminators  offset compensated high gain preamplifier followed by latch Zero suppression logic Memory management Memory IP blocks Readout controller JTAG controller Current Ref. Bias DACs Row sequencer Width: ~350 µm I/O Pads Power supply Pads Circuit control Pads LVDS Tx & Rx CMOS 0.35 µm OPTO technology, Chip size : 13.7 x 21.5 mm 2 Testability: several test points implemented all along readout path  Pixels out (analogue)  Discriminators  Zero suppression  Signal transmission Reference Voltages Buffering for 1152 discriminators PLL, 8b/10b optional  Integration time: ~ 100 µs  R.O. speed: 10 k frames/s  Hit density: ~ 10 6 particles/cm²/s

10 IPHC christine.hu@ires.in2p3.fr 10 October 2010 USTC Radiation Tolerance Improvement Non ionising radiation tolerance High resistivity sensitive volume  faster charge collection  Exploration of a VDSM technology with depleted (partially ~30 µm) substrate: Project "LePix" driven by CERN for SLHC trackers (attractive for CBM, ILC and CLIC Vx Det.)  Exploration of a technology with high resistivity thin epitaxial layer XFAB 0.6 µm techno: ~15 µm EPI (  ~ O(10 3 ) .cm), Vdd = 5 V (MIMOSA25)  Benefit from the need of industry for improvement of the photo-sensing elements embedded into CMOS chip For comparison: standard CMOS technology, low resistivity P-epi high resistivity P-epi: size of depletion zone size is comparable to the P-epi thickness! TCAD Simulation 15 µm high resistivity (1000 Ω. cm) EPI compared to 15 µm standard EPI (10 Ω. cm)

11 IPHC christine.hu@ires.in2p3.fr 11 October 2010 USTC Landau MP (in electrons) versus cluster size 0 n eq /cm² 0.3 x 10 13 n eq /cm² 1.3 x 10 13 n eq /cm² 3 x 10 13 n eq /cm² MIMOSA25 in a high resistivity epitaxial layer 20 μm pitch, + 20°C, self-bias diode @ 4.5 V, 160 μs read-out time Fluence ~ (0.3 / 1.3 / 3·)10 13 n eq /cm 2 Tolerance improved by > 2 order of mag. Need to confirm  det (uniformity !) with beam tests 16x96 Pitch 20µm MIMOSA25 To compare: «standard» non-depleted EPI substrate: MIMOSA15 Pitch=20µm, before and after 5.8x10 12 n eq /cm 2 saturation -> >90 % of charge is collected is 3 pixels -> very low charge spread for depleted substrate EPI: (1000 Ω. Cm)

12 IPHC christine.hu@ires.in2p3.fr 12 October 2010 USTC MIMOSA26 Test Results Laboratory tests:  ENC ~ 11-13 e -  Signal to noise ratio for the seed pixel before irradiation and after exposure to a fluence of 6 x 10 12 n eq / cm² 0.64 mV 0.31 mV

13 IPHC christine.hu@ires.in2p3.fr 13 October 2010 USTC High-Resistivity CMOS Pixel Sensors Preliminary conclusions:  Detection efficiency ~100% (SNR ~40) for very low fake rate: Plateau until fake rate of few 10 -6  Single point resolution <~4 µm  Detection efficiency ~100% after exposure to fluence of 1x10 13 n eq /cm²  Excellent detection performances with high-resistivity epitaxial layer despite moderate resistivity (400 Ω.cm) and poor depletion voltage (<1V)  Tolerance to >~ O(10 14 ) n eq /cm² seems within reach (study under way)  MIMOSA26: design base line for STAR Vx upgrade, CBM MVD. Its performances are close to the ILD vertex detector specifications

14 IPHC christine.hu@ires.in2p3.fr 14 October 2010 USTC Summary of MIMOSA26 Main Characteristics More than 80 sensors tested  Yield ~90% (75% fully functional sensors thinned to 120 µm + 15% (showing one bad row or column)  Thinning yield to 50 µm ~90% Readout time t r.o. ~100 µs (10 4 frames/s)  suited to > 10 6 particules/cm²/s Detection efficiency ~100% (S/N ~ 40) for very low fake rate  Plateau until fake rate of few 10 -6 Single point resolution <~ 4 µm Detection efficiency still ~100% after exposure to:  Fluence of 1x10 13 n eq / cm²  Tolerance to >~O(10 14 ) n eq /cm² seems within reach (study under way)  TID: ~ several 10² KRad at room temperature  Expected to reach ~O(1) MRad tolerance at negative temperature

15 IPHC christine.hu@ires.in2p3.fr 15 October 2010 USTC STAR Heavy Flavor Tracker (HFT) Upgrade Physics Goals:  Identification of mid rapidity Charm and Beauty mesons and baryons through direct reconstruction and measurement of the displaced vertex with excellent pointing resolution TPC – Time Projection Chamber (main detector in STAR) HFT – Heavy Flavor Tracker SSD – Silicon Strip Detector IST – Inner Silicon Tracker PXL – Pixel Detector (PIXEL) Goal: Increasing pointing resolution from the outside in TPCSSDIST PXL ~1 mm~300 µm~250 µm vertex <30 µm courtesy of M. Szelezniak / Vertex-2010

16 IPHC christine.hu@ires.in2p3.fr 16 October 2010 USTC STAR PIXEL Detector ~20 cm Cantilevered support One of two half cylinders RO buffers / drivers Total: 40 ladders Ladder = 10 MAPS sensors (~2x2 cm² each) Detector extraction at one end of the cone Sensors Requirements Multiple scattering minimisation:  Sensors thinned to 50 um, mounted on a flex kapton/aluminum cable  X/X 0 = 0.37% per layer Sufficient resolution to resolve the secondary decay vertices from the primary vertex  < 10 um Luminosity = 8 x 10 27 / cm² / s at RHIC_II  ~200-300 (600) hits / sensor (~4 cm 2 ) in the integration time window  Shot integration time ~< 200 µs Low mass in the sensitive area of the detector  airflow based system cooling  Work at ambient (~ 35 °C ) temperature  Power consumption ~ 100 mW / cm² Sensors positioned close (2.5 - 8 cm radii) to the interaction region  ~ 150 kRad / year  few 10 12 N eq / cm² / year 2.5 cm Inner layer 8 cm radius Outer layer End view Centre of the beam pipe courtesy of M. Szelezniak / Vertex-2010

17 IPHC christine.hu@ires.in2p3.fr 17 October 2010 USTC STAR PIXEL Detector 3 steps evolution:  2007: A MimoSTAR-2 sensors based telescope has been constructed and performed measurements of the detector environment at STAR MimoSTAR-2: sensor with analogue output  2012: The engineering prototype detector with limited coverage (1/3 of the complete detector surface), equipped with PHASE-1 sensors will be installed PHASE-1: sensor with binary output without zero suppression  2013: The pixel detector composed with 2 layers of ULTIMATE sensors will be installed ULTIMATE: sensor with binary output and with zero suppression logic PIXEL detector composed of 2 MAPS layers Prototype detector composed of 3 sectors with PHASE-1 sensors 3 plans telescope with MImoSATR-2 sensors

18 IPHC christine.hu@ires.in2p3.fr 18 October 2010 USTC ULTIMATE: Extension of MIMOSA26 Optimisation 20240 µm 22710 µm 3280 µm 21560 µm 13780 µm MIMOSA26 ULTIMATE Reduction of power dissipation Pixel adjustment & optimisation for a 20.7 µm pixel pitch Discriminator timing diagram optimisation Integration of on-chip voltage regulators Zero Suppression circuit (SuZe) adapted to STAR condition Minimisation of digital to analogue coupling Enhance testability In future chip :Latch up free memory may be integrated  ULTIMATE sensors are planned to be delivered to LBL in Q1 2011

19 IPHC christine.hu@ires.in2p3.fr 19 October 2010 USTC Direct Applications of MIMOSA26 (DUT) Pixel Sensor FP6 project EUDET: Provide to the scientific community an infrastructure aiming to support the detector R&D for the ILC  JRA1: High resolution pixel beam telescope Two arms each equipped with 3 MIMOSA26 (50 µm) DUT between these arms and moveable via X-Y table  Telescope features: High extrapolated resolution < 2 µm Large sensor area ~ 2 cm 2 High read-out speed ~ 10 k frame/s  EUDET telescope is available to use it for tests at test beams, mainly at DESY or CERN Spin-offs  Several BT copies: foreseen for detector R&D  BT for channelling studies, mass spectroscopy, etc  CBM (FAIR): demonstrator for CBM-MVD CBM (Compressed Baryonic Matter)  FIRST (GSI): VD for hadrontherapy  measurements FIRST (Fragmentation of Ions Relevant for Space and Therapy)

20 IPHC christine.hu@ires.in2p3.fr 20 October 2010 USTC Extension of MIMOSA26 to Other Projects STAR HFT (Heavy Flavour Tracker) - PIXEL sensor : (see following slides) Micro Vertex Detector (MVD) of the CBM :  2 double-sided stations equipped with MIMOSA sensors  0.3-0.5% Xo per station  ~< 5 µm single point resolution  Several MRad & > 10 13 n eq /cm²/s  Sensor with double-sided read-out  r.o. speed !  Start of physics >~ 2016 Vertex detector of the ILC:  Geometry: 3 double-sided or 5 single sided layers  ~0.2% Xo total material budget per layer  2 μm (4-bit ADC ) <  sp < 3 μm (discri.) (~16 µm pitch)  t int. ~ 25 μs (innermost layer)  double-sided readout  t int. ~ 100 μs (outer layer)  Single-sided readout  P diss < (0.1–1 W/cm²)× 1/50 duty cycle Candidate for other experiments:  (VD) EIC, (ITS upgrade, FOCAL) ALICE, (SVT) SuperB, (VD) CLIC …

21 IPHC christine.hu@ires.in2p3.fr 21 October 2010 USTC R&D Directions: Sensor Integration in Ultra Light Devices PLUME (Pixelated Ladder with Ultra-low Material Embedding) Project  Study a double-sided detector ladder motivated by the R&D for ILD VD  Targeted material budget: <~0.3%X O  Correlated hits  reconstruct minivector Better resolution / easier alignment  Sensors with different functionalities on each side Square pixels for single point resolution Elongated pixels for time resolution SERWIETE (SEnsor Raw Wrapped In an Extra Thin Envelope) Project  Motivated by HadronPhysics2, FP7  30 µm thin sensors mounted on a thin flex cable and wrapped in polymerised film  Expected material budget <~ 0.15 % Xo  Unsupported & flexible detector layer ? to evaluate the possibility of mounting a supportless ladder on a cylindrical surface like a beam pipe (used as mechanical support). Proof of principle expected in 2012 Collaboration with IMEC Fully functional microprocessor chip in flexible plastic envelope. Courtesy of Piet De Moor, IMEC company, Belgium

22 IPHC christine.hu@ires.in2p3.fr 22 October 2010 USTC R&D Directions: Large Area Sensors (LAS) Large surface detector  minimize dead zone  AIDA, CBM, EIC, biomedical imaging: sensor well beyond the reticle size Maximum size of a CMOS chip in modern deep submicron technology is limited by its reticle size (2x2 cm²) Reticle size is a maximum size that can be realised in a single lithography step  Fabrication using stitching technique Stitching technique:  Large CMOS sensor is divided into smaller sub-blocks  These blocks have to be small enough that they all fit into the limited reticle space  The complete sensor chips are being stitched together from the building blocks in the reticle.

23 IPHC christine.hu@ires.in2p3.fr 23 October 2010 USTC R&D Directions: Using 3DIT to Achieve Ultimate MAPS Performances 3DIT: stack thin (~10 µm) IC chips (wafers), inter- connections between chips by TSV 3DIT are expected to be particularly beneficial for MAPS  Combine different fabrication processes  Resorb most limitations specific to 2D MAPS Split signal collection and processing functionalities, use best suited technology for each Tier :  Tier-1: charge collection system  Epitaxy (depleted or not), deep N-well ?  ultra thin layer  X 0   Tier-2: analogue signal processing  analogue, low I leak, process (number of metal layers)  Tier-3: mixed and digital signal processing  Tier-4: data formatting (electro-optical conversion ?) digital process (number of metal layers) feature size  fast laser driver, etc. Analog Readout Circuit Diode Pixel Controller, A/D conversion Pixel Controller, CDS Digital Analog Sensor ~ 50 µm Analog Readout Circuit Diode ~ 20 µm Analog Readout Circuit Diode Analog Readout Circuit Diode TSV Through Silicon Vias 2D - MAPS 3D - MAPS RTI international Infrared Imager The First 3D Multiproject Run for HEP International Collaboration USA, France, Italy, Germany, …

24 IPHC christine.hu@ires.in2p3.fr 24 October 2010 USTC IPHC 3D MAPS: Self Triggering Pixel Strip-like Tracker (STriPSeT) Combination of 2 processes: Tezzaron/Chartered 2-tiers with a high resistivity EPI tier  Tier-1: Thin, depleted (high resistivity EPI) detection tier  ultra thin sensor!!! Fully depleted  Fast charge collection (~5ns)  should be radiation tolerant For small pitch, charge contained in less than two pixels Sufficient (rather good) S/N ratio defined by the first stage “charge amplification” ( >x10) by capacitive coupling to the second stage  Tier-2: Shaperless front-end: Single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop  Shaping time of ~200 ns very convenient: good time resolution Low offset, continuous discriminator  Tier-3: Digital: Data driven (self-triggering), sparsified binary readout, X and Y projection of hit pixels pattern Matrix 256x256  2 µs readout time Tier-1Tier-2Tier-3 Cd~10fF G~1 Cc=100fF Cf~10fF  off <10 mV Digital RD Vth Ziptronix (Direct Bond Interconnect, DBI®*) Tezzaron (metal-metal (Cu) thermocompression)  DBI® – Direct Bond Interconnect, low temperature CMOS compatible direct oxide bonding with scalable interconnect for highest density 3D interconnections ( 10 8 /cm /cm² Possible)

25 IPHC christine.hu@ires.in2p3.fr 25 October 2010 USTC IPHC 3D MAPS: Fast 3D Sensor with Power Reduction MAPS with fast pipeline digital readout aiming to minimise power consumption (R&D in progress)  Subdivide sensitive area in ”small” matrices running individually in rolling shutter mode  Adapt the number of raws to required frame readout time  few µs r.o. time may be reached  Design in 20 µm²: Tier 1: Sensor & preamplifier (G ~ 500 µV/e - ) Tier 2: 4-bit pixel-level ADC with offset cancellation circuitry (LSB ~ N) Tier 3: Fast pipeline readout with data sparsification   sp ~ 2 μm T int. < 10 µs ~18-20 µm Detection diode & Amplifier 4-bit ADC RO Sparsification

26 IPHC christine.hu@ires.in2p3.fr 26 October 2010 USTC Conclusion After 10 year, 2D-MAPS R&D reaches its maturity for real scale applications  EUDET, STAR (PIXEL), FIRST (VD), … R&D continues: new performance scale accessible with emergent CMOS fabrication technology allowing to fully exploit the potential of MAPS approach  CBM, ALICE/LHC, EIC, CLIC, SuperB, …  System integration (PLUME, SERWIETE) + Intelligent data processing + data transmission Mediate & long term objective: 3D sensors mainly motivated by RO < few µs  Ultimately: expect to become the best performing pixel technology ever …?

27 IPHC christine.hu@ires.in2p3.fr 27 October 2010 USTC Back up

28 IPHC christine.hu@ires.in2p3.fr 28 October 2010 USTC Application of CMOS Sensors to CBM Experiment

29 IPHC christine.hu@ires.in2p3.fr 29 October 2010 USTC Direct Applications of EUDET Sensor

30 IPHC christine.hu@ires.in2p3.fr 30 October 2010 USTC MIMOSA26 Test Standard EPI layer (fab. end 2008) v.s. high resistivity EPI layer (fab. end 2009) Charge collection & S/N (Analogue output, Freq. 20 MHz) EPI layer Standard (~10 .cm) 14 µm High resistivity (~400 .cm) Charge Collection ( 55 Fe source) Seed2x23x3EPIseed2x23x3 ~21%~ 54 %~ 71 % 10 µm~ 36 %~ 85 %~ 95 % 15 µm~ 31 %~ 78 %~ 91 % 20 µm~ 22 %~ 57 %~ 76 % S/N at seed pixel ( 106 Ru source) ~ 20 (230 e - /11.6 e - ) 10 µm~ 35 15 µm~ 41 20 µm~ 36 0.64 mV 0.31 mV ENC ~ 13-14 e -


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