A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline.

Name: A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline.
Uploaded: 2017-07-13T13:28:08+00:00
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Description: A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline.

A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline Prominent features of MAPS (Monolithic Active Pixel Sensors) Fast readout architecture & test results CMOS Pixel Sensors' Applications STAR HFT upgrade: PIXEL detector Current R&D of CMOS Pixel Sensors in Strasbourg Summary + Perspectives

Development of MAPS for Charged Particle Tracking
Original aspect: Integration of sensitive volume (EPI: epitaxial layer) and front-end read-out electronics on the same substrate Charge created in EPI layer, excess carries propagate thermally, collected by NWELL/PEPI diodes, with help of reflection on boundaries with P-well and substrate (high doping) Q = 80 e-h / µm  signal < 1000 e- High granularity, compact, flexible, EPI layer ~10-20 µm thick Thinning to ~30–40 µm permitted Standard CMOS fabrication technology Cheap, fast multi-project run turnaround Room temperature operation ~35 °C Ionizing Particle Attractive balance between granularity, material budget, radiation tolerance, read out speed and power dissipation 18-20/10/ ATHIC 2010 IPHC

High Readout Speed Sensors Architecture
Design according to 3 main issues: Increasing S/N at pixel-level Pre-amp and CDS in each pixel A to D Conversion at column-level 1 discriminator / column Offset + FPN compensations Zero suppression at chip edge level Reduce the raw data flow of MAPS Data compression factor ranging from 10 to1000, depending on the hit density per frame On-chip bias DAC, voltage regulators Remote and programmable controller Low Power vs. High Speed Power  Readout in a rolling shutter mode Speed  Pixels belonging 1 row are read out simultaneously Pixel Array Analogue processing / pixel Column-level ADC Zero Suppression + Memories Bias DAC Contrl. + Data trans. Implemented in chip periphery IPHC (IN2P3) & IRFU (CEA) collaboration 18-20/10/ ATHIC 2010 IPHC

MIMOSA26: 1st Sensor with Integrated zero suppression
Chip size : x mm² Standard resistivity (10Ω.cm) EPI High resistivity (400Ω.cm) EPI CMOS 0.35 µm Technology Pixel array: 576 x 1152  0.7 million pixels pitch: 18.4 µm Active area: ~10.6 x 21.2 mm2 In each pixel: Amplification + CDS 1152 column-level discriminators offset compensated high gain preamplifier followed by latch Zero suppression logic I/O Pads Power supply Pads Circuit control Pads LVDS Tx & Rx Readout controller JTAG controller Memory management Memory IP blocks 18-20/10/ ATHIC 2010 IPHC

MIMOSA26 Test Results Laboratory tests: ENC ~ 11-13 e-
Signal to noise ratio for the seed pixel before irradiation and after exposure to a fluence of 6 x 1012 neq / cm² 0.64 mV 0.31 mV 18-20/10/ ATHIC 2010 IPHC

MIMOSA26 Test Results (2) M.i.p. detection with CMOS sensors combined in a Beam telescope (BT) 4 EUDET ref. sensors & 2 sensors under test Tested at CERN-SPS (120 GeV pions) Sensor variants: Standard EPI (~10 Ω.cm, 14 µm thick) High Resistivity EPI (~400 Ω.cm), 10 & 15 µm thick Top ~20°C HR-15 HR-10 1x1013 neq/cm² 18-20/10/ ATHIC 2010 IPHC

Summary of MIMOSA26 Main Characteristics
More than 80 sensors tested Yield ~90% (75% fully functional sensors thinned to 120 µm + 15% (showing one bad row or column) Thinning yield to 50 µm ~90% Readout time tr.o.~100 µs (10 4 frames/s)  suited to >~ 10 6 particules/cm²/s Detection efficiency ~100% (S/N ~ 40) for very low fake rate Plateau until fake rate of few 10-6 Single point resolution <~ 4 µm Detection efficiency still ~100% after exposure to: Fluence of 1x1013 neq / cm²  Tolerance to >~O(1014) neq /cm² seems within reach (study under way) TID: ~ several 10² KRad at room temperature  Expected to reach ~O(1) MRad tolerance at negative temperature 18-20/10/ ATHIC 2010 IPHC

Outline Prominent MAPS (CMOS Pixel Sensors) features
Main architecture & test results CMOS Pixel Sensors' Applications STAR HFT upgrade: PIXEL detector Current R&D of CMOS Pixel Sensors in Strasbourg Summary + Perspectives 18-20/10/ ATHIC 2010 IPHC

Direct Applications of MIMOSA26
FP6 project EUDET: Provide to the scientific community an infrastructure aiming to support the detector R&D for the ILC JRA1: High resolution pixel beam telescope Two arms, each equipped with 3 MIMOSA26 (50 µm) DUT between these arms and moveable via X-Y table Telescope features: High extrapolated resolution < 2 µm Large sensor area ~ 2 cm2 High read-out speed ~ 10 k frame/s EUDET telescope is available to use it for tests at test beams, mainly at DESY or CERN Spin-offs Several BT copies: foreseen for detector R&D BT for channelling studies, mass spectroscopy, etc CBM (FAIR): demonstrator for CBM-MVD CBM (Compressed Baryonic Matter) FIRST (GSI): VD for hadrontherapy  measurements FIRST (Fragmentation of Ions Relevant for Space and Therapy) (DUT) Pixel Sensor 18-20/10/ ATHIC 2010 IPHC

Extension of MIMOSA26 to Other Projects
STAR HFT (Heavy Flavour Tracker) - PIXEL sensor : (see following slides) Micro Vertex Detector (MVD) of the CBM : 2 double-sided stations equipped with MIMOSA sensors % Xo per station ~< 5 µm single point resolution Several MRad & > 1013neq /cm²/s Sensor with double-sided read-out r.o. speed ! Start of physics >~ 2016 Vertex detector of the ILC: Geometry: 3 double-sided or 5 single sided layers Total material budget: ~0.2% Xo per layer 2 μm (4-bit ADC ) < sp < 3 μm (discri.) (~16 µm pitch) tint. ~ 25 μs (innermost layer)  double-sided readout tint. ~ 100 μs (outer layer)  Single-sided readout Pdiss < (0.1–1 W/cm²)× 1/50 duty cycle Candidate for other experiments: (VD) EIC, (ITS upgrade, FOCAL) ALICE, (SVT) SuperB, (VD) CLIC … ILD design 18-20/10/ ATHIC 2010 IPHC

STAR Heavy Flavor Tracker (HFT) Upgrade
Physics Goals: Identification of mid rapidity Charm and Beauty mesons and baryons through direct reconstruction and measurement of the displaced vertex with excellent pointing resolution TPC – Time Projection Chamber (main detector in STAR) HFT – Heavy Flavor Tracker SSD – Silicon Strip Detector IST – Inner Silicon Tracker PXL – Pixel Detector (PIXEL) courtesy of M. Szelezniak / Vertex-2010 The HFT is a tracking upgrade to the STAR detector to identify mid rapidity Charm and Beauty mesons and baryons through direct reconstruction and measurement of the displaced vertex with excellent pointing resolution. Goal: Increasing pointing resolution from the outside in TPC SSD IST PXL ~1 mm ~300 µm ~250 µm vertex <30 µm 18-20/10/ ATHIC 2010 IPHC

STAR PIXEL Detector Sensor Requirements
Multiple scattering minimisation: Sensors thinned to 50 um, mounted on a flex kapton/aluminum cable  X/X0 = 0.37% per layer Sufficient resolution to resolve the secondary decay vertices from the primary vertex < 10 um Luminosity = 8 x 1027 / cm² / s at RHIC_II ~ (600) hits / sensor (~4 cm2) in the integration time window Shot integration time ~< 200 µs Low mass in the sensitive area of the detector  airflow based system cooling Work at ambient (~ 35 °C ) temperature Power consumption ~ 100 mW / cm² Sensors positioned close ( cm radii) to the interaction region ~ 150 kRad / year few 1012 Neq / cm² / year Total: 40 ladders Ladder = 10 sensors (~2x2 cm² each) RO buffers / drivers Cantilevered support ~20 cm One of two half cylinders Detector extraction at one end of the cone 8 cm radius Outer layer 2.5 cm Inner layer End view Centre of the beam pipe courtesy of M. Szelezniak / Vertex-2010 18-20/10/ ATHIC 2010 IPHC

ULTIMATE: Extension of MIMOSA26
Optimisation Reduction of power dissipation Pixel adjustment & optimisation for a 20.7 µm pixel pitch Discriminator timing diagram optimisation Integration of on-chip voltage regulators Zero Suppression circuit (SuZe) adapted to STAR condition Minimisation of digital to analogue coupling Enhance testability In future chip :Latch up free memory may be integrated  ULTIMATE sensors are planned to be delivered to LBL in Q1 2011 18-20/10/ ATHIC 2010 IPHC

Outline Prominent MAPS (CMOS Pixel Sensors) features
Main architecture & test results CMOS Pixel Sensors' Applications STAR HFT upgrade: PIXEL detector Current R&D of CMOS Pixel Sensors in Strasbourg Summary + Perspectives 18-20/10/ ATHIC 2010 IPHC

R&D Directions: Sensor Integration in Ultra Light Devices
PLUME (Pixelated Ladder with Ultra-low Material Embedding) Project Study a double-sided detector ladder motivated by the R&D for ILD VD Targeted material budget: <~0.3%XO Correlated hits reconstruct mini-vector Resolution / alignment / shallow angle tracks Sensors with different functionalities on each side Square pixels for single point resolution Elongated pixels for time resolution SERWIETE (SEnsor Raw Wrapped In an Extra Thin Envelope) Project Motivated by HadronPhysics2, FP7 30 µm thin sensors mounted on a thin flex cable and wrapped in polymerised film Expected material budget <~ 0.15 % Xo Unsupported & flexible detector layer ? to evaluate the possibility of mounting a supportless ladder on a cylindrical surface like a beam pipe (used as mechanical support). Proof of principle expected in 2012 Collaboration with IMEC Fully functional microprocessor chip in flexible plastic envelope. Courtesy of Piet De Moor, IMEC company, Belgium 18-20/10/ ATHIC 2010 IPHC

R&D Directions: Large Area Sensors (LAS)
Large surface detector  minimize dead zone AIDA, CBM, EIC, biomedical imaging: sensor well beyond the reticle size Maximum size of a CMOS chip in modern deep submicron technology is limited by its reticle size (2x2 cm²) Reticle size is a maximum size that can be realised in a single lithography step Fabrication using stitching technique Stitching technique: Large CMOS sensor is divided into smaller sub-blocks These blocks have to be small enough that they all fit into the limited reticle space The complete sensor chips are being stitched together from the building blocks in the reticle. 18-20/10/ ATHIC 2010 IPHC

R&D Directions: Using 3DIT to Achieve Ultimate MAPS Performances
RTI international Infrared Imager 3DIT: stack thin (~10 µm) IC chips (wafers), interconnections between tiers by TSV 3DIT are expected to be particularly beneficial for MAPS Combine different fabrication processes Resorb most limitations specific to 2D MAPS Split signal collection and processing functionalities, use best suited technology for each Tier : Tier-1: charge collection system  Epitaxy (depleted or not), deep N-well ?  ultra thin layer X0  Tier-2: analogue signal processing analogue, low Ileak, process (number of metal layers) Tier-3: mixed and digital signal processing Tier-4: data formatting (electro-optical conversion ?) digital process (number of metal layers) feature size fast laser driver, etc. Analog Readout Circuit Diode Analog Readout Circuit Diode Sensor Analog Pixel Controller, CDS ~ 50 µm Analog Readout Circuit Diode Analog Readout Circuit Diode Digital TSV Through Silicon Vias ~ 20 µm Pixel Controller, A/D conversion The First 3D Multiproject Run for HEP International Collaboration USA, France, Italy, Germany, … 2D - MAPS 3D - MAPS 18-20/10/ ATHIC 2010 IPHC

IPHC 3D MAPS: Self Triggering Pixel Strip-like Tracker (STriPSeT)
Combination of 2 processes: Tezzaron/Chartered 2-tiers with a high resistivity EPI tier Tier-1: Thin, depleted (high resistivity EPI) detection tier  ultra thin sensor!!! Fully depleted  Fast charge collection (~5ns)  should be radiation tolerant For small pitch, charge contained in less than two pixels Sufficient (rather good) S/N ratio defined by the first stage “charge amplification” ( >x10) by capacitive coupling to the second stage Tier-2: Shaperless front-end: Single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop  Shaping time of ~200 ns very convenient: good time resolution Low offset, continuous discriminator Tier-3: Digital: Data driven (self-triggering), sparsified binary readout, X and Y projection of hit pixels pattern Matrix 256x256  2 µs readout time Tier-1 Tier-2 Tier-3 Cd~10fF G~1 Cc=100fF Cf~10fF off <10 mV Digital RD Vth Ziptronix (Direct Bond Interconnect, DBI®*) Tezzaron (metal-metal (Cu) thermocompression) DBI® – low temperature CMOS compatible direct oxide bonding with scalable interconnect for highest density 3D interconnections (< 1 µm Pitch, > 108/cm /cm² Possible) 18-20/10/ ATHIC 2010 IPHC

IPHC 3D MAPS: Fast 3D Sensor with Power Reduction
MAPS with fast pipeline digital readout aiming to minimise power consumption (R&D in progress) Subdivide sensitive area in ”small” matrices running individually in rolling shutter mode Adapt the number of rows to required frame readout time  few µs r.o. time may be reached Design in 20 µm²: Tier 1: Sensor & preamplifier (G ~ 500 µV/e-) Tier 2: 4-bit pixel-level ADC with offset cancellation circuitry (LSB ~ N) Tier 3: Fast pipeline readout with data sparsification  sp ~ 2 μm Tint. < 10 µs Detection diode & Amplifier 4-bit ADC Spars. RO ~18-20 µm 18-20/10/ ATHIC 2010 IPHC

Summary + Perspectives
2D-MAPS R&D reaches its maturity for real scale applications EUDET, STAR HFT, FIRST VD… R&D continues: new performance scale accessible with emergent CMOS fabrication technology allowing to fully exploit the potential of MAPS approach CBM, ALICE/LHC, EIC, CLIC, SuperB, …  System integration (PLUME , SERWIETE) + Intelligent data processing + data transmission Mediate & long term objective: 3D sensors mainly motivated by Read out time < few µs 18-20/10/ ATHIC 2010 IPHC

Back up slides 18-20/10/2010 ATHIC 2010
IPHC

STAR PIXEL Detector 3 steps evolution:
2007: A MimoSTAR-2 sensors based telescope has been constructed and performed measurements of the detector environment at STAR MimoSTAR-2: sensor with analogue output 2012: The engineering prototype detector with limited coverage (1/3 of the complete detector surface), equipped with PHASE-1 sensors will be installed PHASE-1: sensor with binary output without zero suppression 2013: The pixel detector composed with 2 layers of ULTIMATE sensors will be installed ULTIMATE: sensor with binary output and with zero suppression logic 3 plans telescope with MImoSATR-2 sensors Prototype detector composed of 3 sectors with PHASE-1 sensors PIXEL detector composed of 2 MAPS layers 18-20/10/ ATHIC 2010 IPHC

MIMOSA26 with high resistivity EPI layer (1)
Charge collection efficiency for the seed pixel, and for 2x2 and 3x3 pixel clusters Signal to noise ratio for the seed pixel before irradiation and after exposure to a fluence of 6 x 1012 neq / cm² 18-20/10/ ATHIC 2010 IPHC

MIMOSA26 with high resistivity EPI layer (2)
Beam test at CERN SPS (120 GeV pions) Test conditions: 50 MHz to emulate the longer integration time in ULTIMATE 35 °C temperature! resolution < 5um 18-20/10/ ATHIC 2010 IPHC

Achieved Performances with Analogue Readout
MAPS provide excellent tracking performances Detection efficiency ~100% ENC ~10-15 e- S/N > (MPV) at room temperature Single point resolution ~ µm, a function of pixel pitch ~ 1 µm (10 µm pitch), ~ 3 µm (40 µm pitch) MAPS: Final chips: MIMOTEL (2006): ~66 mm², 65k pixels, 30 µm pitch EUDET Beam Telescope (BT) demonstrator MIMOSA18 (2006): ~37 mm², 262k pixels, 10 µm pitch High resolution EUDET BT demonstrator MIMOSTAR (2006): ~2 cm², 204k pixels, 30 µm pitch Test sensor for STAR Vx detector upgrade LUSIPHER (2007): ~40 mm², 320k pixels, 10 µm pitch Electron-Bombarded CMOS for photon and radiation imaging detectors MIMOSTAR Chip dimension: ~2 cm² MIMOTEL M18 LUSIPHER 18-20/10/ ATHIC 2010 IPHC

Radiation tolerance (preliminary)
Ionising radiation tolerance: O(1 M Rad) (MIMOSA15, test cond. 5 GeV e-, T = -20°C, tint~180 µs) tint << 1 ms, crucial at room temperature Non ionising radiation tolerance: depends on pixel pitch: 20 µm pitch: 2x1012 neq /cm2 , (Mimosa15, tested on DESY e- beams, T = - 20°C, tint ~700 μs) 5.8·1012neq/cm² values derived with standard and with soft cuts 10 µm pitch: 1013 neq /cm2 , (MIMOSA18, tested at CERN-SPS , T = - 20°C, tint ~ 3 ms) parasitic 1–2 kGy gas  N ↑ Further studies needed : Tolerance vs diode size, Readout speed, Digital output, ... , Annealing ?? Integ. Dose Noise S/N (MPV) Detection Efficiency 9.0 ± 1.1 27.8 ± 0.5 100 % 1 Mrad 10.7 ± 0.9 19.5 ± 0.2 99.96 % ± 0.04 % Fluence (1012neq/cm²) 0.47 2.1 5.8 (5/2) 5.8 (4/2) S/N (MPV) 27.8 ± 0.5 21.8 ± 0.5 14.7 ± 0.3 8.7 ± 2. 7.5 ± 2. Det. Efficiency (%) 100. 99.9 ± 0.1 99.3 ± 0.2 77. ± 2. 84. ± 2. Fluence (1012neq/cm²) 6 10 Q cluster (e-) 1026 680 560 S/N (MPV) 28.5 ± 0.2 20.4 ± 0.2 14.7 ± 0.2 Det. Efficiency (%) 99.93 ± 0.03 99.85 ± 0.05 99.5 ± 0.1 18-20/10/ ATHIC 2010 IPHC

System integration Industrial thinning (via STAR collaboration at LBNL) ~50 µm, expected to ~30-40 µm Ex. MIMOSA18 (5.5×5.5 mm² thinned to 50 μm) Development of ladder equipped with MIMOSA chips (coll. with LBNL) STAR ladder (~< 0.3 % X0 )  ILC (<0.2 % X0 ) Edgeless dicing / stitching  alleviate material budget of flex cable 18-20/10/ ATHIC 2010 IPHC

MAPS performance Improvement
MIMOSA22 Pixel array 136 x 576 pitch 18.4 µm 128 discriminators R&D organisation : 4 (5) simultaneous prototyping lines Pixel Array Analogue processing / pixel A/D: 1 ADC ending each column Zero suppression Bias DC-DC Data transmission Architecture of pixel array organised in // columns read out: Pre-amp and CDS in each pixel A/D: 1 discriminator / column (offset compensation) Power vs Speed Power  Readout in a rolling shutter mode Speed  Pixels belonging to the same row are read out simultaneously MIMOSA8 (2004), MIMOSA16 (2006), MIMOSA22 (2007/08) Zero suppression circuit: Reduce the raw data flow of MAPS Data compression factor ranging from 10 to 1000, depending on the hit density per frame SUZE-01 (2007) 4–5 bits ADCs (~103 ADC per sensor) Potentially replacing column-level discriminators 5 bits: sp ~1.7–1.6 µm 4 bits: sp < 2 µm for 20 µm pitch Next step: integrate column-level ADC with pixel array SUZE-01 5-bit ADC Serial link transmission with clock recovery Prototype ( ) Voltage regulator & DC-DC converter 18-20/10/ ATHIC 2010 IPHC

P- EPI 18-20/10/2010 ATHIC 2010 IPHC christine.hu@ires.in2p3.fr Pixel
N-well P-well P- EPI Substrate P++ Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel P-well N-well P- EPI Substrate P++ 18-20/10/ ATHIC 2010 IPHC

IPHC christine.hu@ires.in2p3.fr
Spatial resolution Time resolution 18-20/10/ ATHIC 2010 IPHC

Excellent detection performances with High resistivity EPI layer !
18-20/10/ ATHIC 2010 IPHC

A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline.

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A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline.

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Presentation on theme: "A High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade Christine Hu-Guo on behalf of the IPHC (Strasbourg) CMOS Sensors group Outline."— Presentation transcript:

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