1. Spring 08, Jan 22.. ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Verification Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr078/course.html

2. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)2 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development Design Manufacture

3. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)3 Origin of “Debugging” D. Gizopoulos (Editor), Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006, Chapter 3, “Silicon Debug,” by D. Josephson and B. Gottlieb. Thomas Edison wrote in a letter in 1878: “It has been just so in all of my inventions. The first step is an intuition, and comes with a burst, then difficulties arise—this thing gives out and [it is] then that “Bugs” — as such little faults and difficulties are called — show themselves and months of intense watching, study and labor are requisite before commercial success or failure is certainly reached.” An interesting example of “debugging” was in 1945 when a computer failure was traced down to a moth that was caught in a relay between contacts (Figure 3-1).

4. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)4 Verification and Testing Specification Testing Manufacturing Verification Hardware design Silicon 50-70% cost30-50% cost

5. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)5 Definitions  Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.  Alternative Definition: Verification is a process used to demonstrate the functional correctness of a design.

6. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)6 What is Being Verified?  Given a set of specification,  Does the design do what was specified? Specification Interpretation RTL coding Verification J. Bergeron, Writing Testbenches: Functional Verification Of HDL Models, Springer, 2000.

7. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)7 Avoiding Interpretation Error  Use redundancy Specification Interpretation RTL coding Verification Interpretation

8. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)8 Methods of Verification  Simulation: Verify input-output behavior for selected cases.  Formal verification: Exhaustively verify input- output behavior:  Equivalence checking  Model checking  Symbolic simulation

9. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)9 Equivalence Checking  Logic equivalence: Two circuits implement identical Boolean function.  Logic and temporal equivalence: Two finite state machines have identical input-output behavior (machine equivalence).  Topological equivalence: Two netlists are identical (graph isomorphism).  Reference: S.-Y. Hwang and K.-T. Cheng, Formal Equivalence Checking and Design Debugging, Springer, 1998.

10. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)10 Compare Two Circuits  Graphs isomorphic?  Boolean functions identical?  Timing behaviors identical? a c b a c b ff

11. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)11 Model Checking  Construct an abstract model of the system, usually in the form of a finite-state machine (FSM).  Analytically prove that the model does not violate the properties (assertions) of original specification.  Reference: E. M. Clarke, Jr., O. Grumberg, and D. A. Peled, Model Checking, MIT Press, 1999. Specification Interpretation RTL coding Model checking Assertions RTL

12. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)12 Symbolic Simulation  Simulation with algebraic symbols rather than numerical values.  Self-consistency: A complex (more advanced) design produces the same result as a much simpler (and previously verified) design.  Reference: R. B. Jones, Symbolic Simulation Methods for Industrial Formal Verification, Springer, 2002.

13. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)13 Simulation: Testbench Design under verification (HDL) Testbench (HDL)

14. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)14 Testbench  HDL code:  Generates stimuli  Checks output responses  Approaches:  Blackbox  Whitebox  Greybox  Metrics (unreliable):  Statement coverage  Path coverage  Expression or branch coverage

15. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)15 Equivalence Checking  Definition: Establishing that two circuits are functionally equivalent.  Applications:  Verify that a design is identical to specification.  Verify that synthesis did not change the function.  Verify that corrections made to a design did not create new errors.

16. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)16 Compare Two Circuits  Are graphs isomorphic?Yes  Else, are Boolean functions identical?Yes  Then, are timing behaviors identical?Yes a c b a c b ff

17. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)17 ATPG Approach (Miter)   Redundancy of a stuck-at-0 fault, checked by ATPG, establishes equivalence of the corresponding output pair.   If the fault is detectable, its tests are used to diagnose the differences. Circuit 1 (Verified design) Circuit 2 (Sythesized or modified design) stuck-at-0

18. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)18 Difficulties with Miter  ATPG is NP-complete  When circuits are equivalent, proving redundancy of faults is computationally expensive.  When circuits are different, test vectors are quickly found, but diagnosis is difficult.

19. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)19 A Heuristic Approach  Derive V1, test vectors for all faults in C1.  Derive V2, test vectors for all faults in C2.  If the combined set, V1+V2, produces the same outputs from the two circuits, then they are probably equivalent.  Reference: V. D. Agrawal, “Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation,” Proc. 13 th International Conf. VLSI Design, January 2000, pp. 306-311.

20. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)20 Example Circuit C1 x1 x2 x3 x4 C1 C1 = x1 x3 x4 + x2 x3 + x2 x4 111 1111 1 x3 x2 x4 x1 Tests

21. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)21 Example Circuit C2 x1 x2 x3 x4 C2 C2 = x1 x3 x4 + x2 x3 + x2 x4 111 1111 1 x3 x2 x4 x1 Tests

22. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)22 C1 ≡ C2 111 1111 1 x3 x2 x4 x1 Tests 111 1111 1 x3 x2 x4 x1 Tests C1 C2

23. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)23 C2’: Erroneous Implementation of C2 x1 x2 x3 x4 C2’ C2 = x1 x3 x4 + x2 x3 + x2 x4 111 111 1 x3 x2 x4 x1 Tests C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4 minterm deleted

24. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)24 Incorrect Result: C1 ≡ C2’ C1 = x1 x3 x4 + x2 x3 + x2 x4 111 111 1 x3 x2 x4 x1 Tests C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4 minterm deleted 111 1111 1 x3 x2 x4 x1 Tests

25. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)25 Additional Safeguard   Simulate V1+V2 for equivalence:   Output always 0   No single fault on PI’s detected   Still not perfect C1 (Verified design) C2 (Sythesized or modified design) s-a-0 s-a-1 0

26. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)26 Probabilistic Equivalence  Consider two Boolean functions F and G of the same set of input variables {X1,..., Xn}.  Let f = Prob(F=1), g = Prob(G=1), xi = Prob(Xi=1)  For any arbitrarily given values of xi, if f = g, then F and G are equivalent with probability 1.  References:  J. Jain, J. Bittner, D. S. Fussell and J. A. Abraham, “Probabilistic Verification of Boolean Functions,” Formal Methods in System Design, vol. 1, pp 63-117, 1992.  V. D. Agrawal and D. Lee, “Characteristic Polynomial Method for Verification and Test of Combinational Circuits,” Proc. 9 th International Conf. VLSI Design, January 1996, pp. 341-342.

27. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)27 Simplest Example  F = X1.X2, f = x1 x2  G = X1+X2, g = (1 – x1)(1 – x2) = 1 – x1 – x2 + x1 x2 = 1 – x1 – x2 + x1 x2  Input probabilities, x1 and x2, are randomly taken from {0.0, 1.0}  We make a wrong decision if f = g, i.e., x1x2 = 1 – x1 – x2 + x1 x2 orx1 + x2 = 1

28. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)28 Probability of Wrong Decision x1 x2 0 Randomly selected point (x1,x2) x1 + x2 = 1 1.0 Probability of wrong decision = Random point falls on line {x1 + x2 = 1} = (area of line)/(area of unit square) = 0

29. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)29 Calculation of Signal Probability  Exact calculation  Exponential complexity.  Affected by roundoff errors.  Alternative: Monte Carlo method  Randomly select input probabilities  Generate random input vectors  Simulate circuits F and G  If outputs have a mismatch, circuits are not equivalent.  Else, stop after “sufficiently” large number of vectors (open problem).

30. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)30 References on Signal Probability  S. C. Seth and V. D. Agrawal, “A New Model for Computation of Probabilistic Testability in Combinational Circuits,” INTEGRATION, The VLSI Journal, vol. 7, pp. 49-75, 1989.  V. D. Agrawal and D. Lee and H. Woźniakowski, “Numerical Computation of Characteristic Polynomials of Boolean Functions and its Applications,” Numerical Algorithms, vol. 17, pp. 261-278, 1998.

31. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)31 More on Equivalence Checking  Don’t cares  Sequential circuits  Time-frame expansion  Initial state  Design debugging (diagnosis)  Reference: S.-Y. Hwang and K.-T. Cheng, Formal Equivalence Checking and Design Debugging, Springer, 1998.

32. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)32 Methods of Equivalence Checking  Satisfiability algorithms  ATPG methods  Binary decision diagrams (BDD)

33. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)33 Shannon’s Expansion Theorem  C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Trans. AIEE, vol. 57, pp. 713-723, 1938.  Consider:  Boolean variables, X1, X2,..., Xn  Boolean function, F(X1, X2,..., Xn)  Then F = Xi F(Xi=1) + Xi’ F(Xi=0)  Where  Xi’ is complement of Xi  Cofactors, F(Xi=j) = F(X1, X2,.., Xi=j,.., Xn), j = 0 or 1

34. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)34 Theorem (1)F = Xi F(Xi=1) + Xi’ F(Xi=0) ∀ i=1,2,3,... n (2)F = (Xi + F(Xi=0)) (Xi’ + F(Xi=1)) ∀ i=1,2,3,... n F Xi F(Xi=0) F(Xi=1) 0 1

35. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)35 Expansion About Two Inputs  F = XiXj F(Xi=1, Xj=1) + XiXj’ F(Xi=1, Xj=0) + Xi’Xj F(Xi=0, Xj=1) + Xi’Xj’ F(Xi=0, Xj=0)  In general, a Boolean function can be expanded about any number of input variables.  Expansion about k variables will have 2 k terms.

36. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)36 Binary Decision Tree a c b f a bb c ccc 00100111 0 1 0 0 0 0 1 111 1 1 0 0 Graph representation of a Boolean function. Leaf nodes

37. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)37 Binary Decision Diagrams  Binary decision diagram (BDD) is a graph representation of a Boolean function, directly derivable from Shannon’s expansion.  References:  C. Y. Lee, “Representation of Switching Circuits by Binary Decision Diagrams,” Bell Syst. Tech J., vol. 38, pp. 985-999, July 1959.  S. Akers, “Binary Decision Diagrams,” IEEE Trans. Computers, vol. C-27, no. 6, pp. 509-516, June 1978.  Ordered BDD (OBDD) and Reduced Order BDD (ROBDD).  Reference:  R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677- 691, August 1986.

38. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)38 Binary Decision Diagram  BDD of an n-variable Boolean function is a tree:  Root node is any input variable.  All nodes in a level are labeled by the same input variable.  Each node has two outgoing edges, labeled as 0 and 1 indicating the state of the node variable.  Leaf nodes carry fixed 0 and 1 labels.  Levels from root to leaf nodes represent an ordering of input variables.  If we trace a path from the root to any leaf, the label of the leaf gives the value of the Boolean function when inputs are assigned the values from the path.

39. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)39 Ordered Binary Decision Diagram (OBDD) a c b f a bb cc 01001 1 0 1 0 0 0 1 11 1 0 a bb c ccc 00100111 0 1 0 0 0 01 111 1 1 0 0 Tree OBDD

40. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)40 OBDD With Different Input Ordering a c b f a bb cc 01001 1 0 1 0 0 0 1 11 1 0 c bb a 01 011 0 1 0 0 1 1 0 a 0 1 0 1

41. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)41 Evaluating Function from OBDD  Start at leaf nodes and work toward the root – leaf node functions are 0 and 1.  Function at a node with variable x is f = x’.f(low) + x.f(high) x highlow 01

42. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)42 Cannot Compare Two Circuits a c b a c b ff c bb a 01 011 0 1 0 0 1 1 0 a 0 1 0 1 c b a 01 01 0 1 0 1 0 1

43. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)43 OBDD Graph Isomorphism  Two OBDDs are isomorphic if there is one-to- one mapping between the vertex sets with respect to adjacency, labels and leaf values.  Two isomorphic OBDDs represent the same function.  Two identical circuits may not have identical OBDDs even when same variable ordering is used.  Comparison is possible if:  Same variable ordering is used.  Any redundancies in graphs are removed.

44. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)44 Reduced Order BDD (ROBDD)  Directed acyclic graph (DAG) (*).  Contains just two leaf nodes labeled 0 and 1.  Variables are indexed, 1, 2,... n, such that the index of a node is greater than that of its child (*).  A node has exactly two child nodes, low and high such that low ≠ high.  Graph contains no pair of nodes such that subgraphs rooted in them are isomorphic. * Properties common to OBDD.

45. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)45 ROBDDs a c b a c b ff c b a 0 1 0 1 0 1 1 c b a 0 1 0 1 0 1 1 0 0 Isomorphic graphs

46. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)46 Reduction: OBDD to ROBDD a c b f a bb cc 01001 1 0 1 0 0 0 1 11 1 0 a 1 0 cc bb 0 0 0 0 1 1 1 1 1 0

47. Spring 08, Jan 22..ELEC 7770: Advanced VLSI Design (Agrawal)47 Properties of ROBDD  Unique for given variable ordering – graph isomorphism verifies logic equivalence.  Size (number of nodes) changes with variable ordering – worst-case size is exponential (e.g., integer multiplier).  Other applications: logic synthesis, testing.  For algorithms to derive ROBDD, see  R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677- 691, August 1986.  G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.  S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994.