2. Performed by: Dmitry Sezganov Vitaly Spector Instructor: Stas Lapchev Artyom Borzin Cooperated with: המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering נושא: דו”ח סיכום פרויקט סופי Parallel Compression for JPEG2000 סמסטר חורף 2004 1

3. 2 Abstract  Military satellites gather information – Photography.  Higher resolution means more details – info worth more.  Solution – lossless image compression: JPEG2000 algorithm.  Continuous input DataStream – Real time compression. Project Purpose: Design and implementation of prototype compression system for satellite images.

4. 3 System Architecture  Testing Module – simulates high bit rate camera.  Channel#1 – COMM; Channel#2 – Rocket IO;  Initialize the Generator with a picture.  The Generator sends the picture periodically. Channel #1 Channel #2 Testing Module Compression Module Testing Unit Raw stream Coded stream Coded stream and controls

5. 4 Requirements & Environment Project requirements:  Building multi-unit compression prototype system.  Easy extension.  Input bit rate is 1.2Gbps.  Fast HW implementation. Environment:  Virtex-II Pro Development Board  ADV202 JPEG2000 Video Codec  PC

6. 5 System Block

7. 6 Testing Board (FPGA Block Diagram #1) PPC405 Processor Block Rocket I/O Transceiver TX RX 16 PLB Arbiter RAM Controller PLB PLB2OPB Bridge OPB Arbiter OPB LCD Controller GPIO Controller UART LITE Stream Generator Receiver 1Gbps

8. 7 Compression Controller Board (FPGA Block Diagram #2) PPC405 Processor Block Rocket I/O Transceiver TX RX 16 PLB Arbiter Codec Controller Module (CCM) PLB PLB2OPB Bridge OPB Arbiter OPB LCD Controller GPIO Controller UART LITE To Codec Board 1Gbps