1. Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 3 Microcomputer Systems Design (Embedded Systems)

2. VHDL Part 3 2 Finite State Machines (FSM)  All programmable logic designs can be specified in Boolean form.  However some designs are easier to conceptualize and implement using non- Boolean models.  The State Machine model is one such model.

3. VHDL Part 3 3 FSM  A state machine represents a system as a set of states, the transitions between them, along with the associated inputs and outputs.  So, a state machine is a particular conceptualization of a particular sequential circuit.  State machines can be used for many other things beyond logic design and computer architecture.

4. VHDL Part 3 4 FSM  Any Circuit with Memory Is a Finite State Machine Even computers can be viewed as huge FSMs  Design of FSMs Involves Defining states Defining transitions between states Optimization / minimization

5. VHDL Part 3 5 Definition of Terms  State Diagram Illustrates the form and function of a state machine. Usually drawn as a bubble-and-arrow diagram.  State A uniquely identifiable set of values measured at various points in a digital system.

6. VHDL Part 3 6 Definition of Terms  Next State The state to which the state machine makes the next transition, determined by the inputs present when the device is clocked.  Branch A change from present state to next state.

7. VHDL Part 3 7 Definition of Terms  Mealy Machine A state machine that determines its outputs from the present state and from the inputs.  Moore Machine A state machine that determines its outputs from the present state only.

8. VHDL Part 3 8 Present and Next State  For any given state, there is a finite number of possible next states.  On each clock cycle, the state machine branches to the next state.  One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle. State 2 State 3 State 1 State 0

9. VHDL Part 3 9 Moore Machine Describe Outputs as Concurrent Statements Depending on State Only state 1 / output 1 state 2 / output 2 transition condition 1 transition condition 2

10. VHDL Part 3 10 Mealy Machine Describe Outputs as Concurrent Statements Depending on State and Inputs state 1 state 2 transition condition 1 / output 1 transition condition 2 / output 2

11. VHDL Part 3 11 Moore vs. Mealy FSM (1)  Moore and Mealy FSMs Can Be Functionally Equivalent  Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area

12. VHDL Part 3 12 Moore vs. Mealy FSM (2)  Mealy FSM Computes Outputs as soon as Inputs Change Mealy FSM responds one clock cycle sooner than equivalent Moore FSM  Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is less likely to have a shorter critical path

13. VHDL Part 3 13 Moore FSM Memory (register) Transition function Output function Input: w Present State: y_present Next State: y_next Output: z

14. VHDL Part 3 14 Mealy FSM Memory (register) Transition function Output function Input: w Present State: y Next State Output: z

15. VHDL Part 3 15 Moore FSM - Example  Moore FSM that Recognizes Sequence 10 S0 / 0S1 / 0S2 / 1 0 0 0 1 1 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed S1: “10” observed

16. VHDL Part 3 16 Mealy FSM - Example  Mealy FSM that Recognizes Sequence 10 S0S1 0 / 0 1 / 0 0 / 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed

17. VHDL Part 3 17 Moore & Mealy FSMs – Examples clock input Moore Mealy 0 1 0 0 0 S0 S1 S2 S0 S0 S0 S1 S0 S0 S0

18. VHDL Part 3 18 FSMs in VHDL Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process

19. VHDL Part 3 19 State Encoding Problem  State Encoding Can Have a Big Influence on Optimality of the FSM Implementation No methods other than checking all possible encodings are known to produce optimal circuit Feasible for small circuits only  Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool

20. VHDL Part 3 20 Types of State Encodings  Binary (Sequential) – States Encoded as Consecutive Binary Numbers Small number of used flip-flops Potentially complex transition functions leading to slow implementations  One-Hot – Only One Bit Is Active Number of used flip-flops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs

21. VHDL Part 3 21 Types of State Encodings StateBinary CodeOne-Hot Code S000010000000 S100101000000 S201000100000 S301100010000 S410000001000 S510100000100 S611000000010 S711100000001

22. VHDL Part 3 22 RTL Design Components Datapath Circuit Control Circuit Data Inputs Data Outputs Control Inputs

23. VHDL Part 3 23 Datapath Circuit  Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task  Examples of Resources Adders, Multipliers, Registers, Memories, etc.

24. VHDL Part 3 24 Control Circuit  Controls Data Movements in Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources  Follows Some ‘Program’ or Schedule  Usually Implemented as FSM

25. VHDL Part 3 25 Example  Consider the following algorithm that gives the maximum of two numbers. 0: int x, y, z; 1: while (1) { 2: while (!start); 3: x = A; 4: y = B; 5: if (x >= y) 6: z = x; else 7: z = y; }

26. VHDL Part 3 26 Example – Cont.  Now, consider the following VHDL code that gives the maximum of two numbers. ----------------------------------------------------------------------------------------- entity MAX is generic(size: integer:=4); port( clk, reset, start: in std_logic; x_i, y_i :in std_logic_vector(size-1 downto 0); z_o: out std_logic_vector(size-1 downto 0)); end MAX; architecture behavioral of MAX is type STATE_TYPE is (S0, S1, S2, S3, S4); signal Current_State, Next_State: STATE_TYPE; signal x, y, mux : std_logic_vector (size-1 downto 0):= (others => '0'); signal z_sel, x_ld, y_ld, z_ld : std_logic := '0'; begin

27. VHDL Part 3 27 Example – Cont. ----------------------------------------------- Reg_x: process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then x '0'); else if (x_ld='1') then x <= x_i; end if; end process; ----------------------------------------------- Reg_y: process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then y '0'); else if (y_ld='1') then y <= y_i; end if; end process; ----------------------------------------------- Reg_z_o:process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then z_o '0'); else if (z_ld='1') then z_o <= mux; end if; end process; ----------------------------------------------- Multiplexer: process (x, y, z_sel) begin if (z_sel='0') then mux <= x; elsif (z_sel='1') then mux <= y; end if; end process; -----------------------------------------------

28. VHDL Part 3 28 Example – Cont. ----------------------------------------------- SYNC_PROC: process (CLK, RESET) begin if (RESET='1') then Current_State <= S0; elsif (CLK'event and CLK = '1') then Current_State <= Next_State; end if; end process; ----------------------------------------------- COMB_PROC: process (Current_State, start, x, y, z_sel) begin case Current_State is -------------------------- when S0 =>-- idle if (start='1') then Next_State <= S1; else Next_State <= S0; end if; -------------------------- when S1 =>-- x = x_i & y = y_i x_ld <= '1'; y_ld <= '1'; z_ld <= '0' Next_State <= S2; -------------------------- when S2 =>-- x ≥ y x_ld <= '0'; y_ld <= '0'; if (x >= y ) then Next_State <= S3; else Next_State <= S4; end if; -------------------------- when S3 =>-- z = x z_sel <= '0'; z_ld<=’1’; Next_State <= S0; -------------------------- when S4 =>-- z = y z_sel <= '1'; z_ld<=’1’; Next_State <= S0; end case; end process; ----------------------------------------------

29. VHDL Part 3 29 Now, What’s Next ?!