1. Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 3 MAD MAC 525 8 th February, 2006 Size estimates/Floor plan W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2. MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design (adder test) Floor plan  To be done  Schematic (started)  Layout  Extraction, LVS, post-layout simulation

3. Multiply Accumulate unit (MAC) Executes function AB+C on 16 bit floating point inputs Multiply and add in parallel to greatly speed up operation Rounding is only performed only once so greater accuracy than individual multiply and add functions. MAD MAC accelerates FP16 blending to enable true HDR graphics Bright things can be really bright Dark things can be really dark And the details can be seen in both Overview - MAD MAC 525

4. Block Diagram RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Reg Y Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input Output 16

5. Design Decisions (Week 3): 1) Decided last week on implementation of all blocks: a) Multiplier: Carry save b) Adder: Variable carry select adder c) Leading zero counter: carry save adder to count leading zeros d) Align: n pass shifter e) Normalize: n pass shifter f) Round: incrementer and shifter

6. Floorplan Reg A RegBRegB Register Y Multiplier Align Exp calc Adder Normalize Round Reg C Ld zero

7. Floorplan Estimated area  Registers6000 um sq  Multiplier22000 um sq  Exponent calc7000 um sq  Align15000 um sq  Adder22000 um sq  Normalize20000 um sq  Round4000 um sq  Leading zero counter3000 um sq Total98000 um sq

8. Floorplan Metal Directionality:M1,M2- Local interconnect, Gnd,Vdd M3,M4- Clock, global wiring

9. Updated Estimated Transistor Count Registers (I/O, pipelining,threading)1800 Carry-Save Multiplier4500 Carry-Select Adder/Subtractor3500 Alignment Shifter 1500 Leading 0 Anticipator 600 Normalize3400 Rounding600 Special Cases and Control Logic2000 Total 17900

10. Critical Path RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Reg Y Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input 16

11. Structural Verilog

12. Structural Verilog (contd.)

13. Schematics

14. Problems and Questions? Have tested our verilog using our own testbenches. Not yet been able to verify it with high level simulation. Currently looking into Simulink for a solution. Suggestions from last week: PDP 11 code found online does 32 bit fp arithmetic.

15. Questions?