1. Compiler-Directed instruction cache leakage optimizations Discussed by Discussed by Raid Ayoub CSE D EPARTMENT

2. Outline Power consumption in CMOS Motivation Handling the problem at the compiler level  Breaking the at the loop level  Examining various strategies for turnoff  Loop level optimizations  Experimental results Summary

3. Leakage power in CMOS Leakage Power: power consumed due to subthreshold leakage current Leakage power: 30% of L1 power and 70% of L2 power for 0.13u Reducing leakage power improves battery life times and reliability Leakage power will be increasingly significant (on) (off) SRAM cell Handling leakage power at the circuit level: Putting cell(s) in low leakage mode State destroying mode (Vdd close to 0) Reduces static power dramatically  Destroys state  Incurs time and power overhead during the switch to active mode State preserving mode (lowering Vdd) Reduces static power Preserves stored data  Incurs time and power overhead during the switch to active mode Vdd

4. Handling Leakage power of caches Challenges in managing leakage-control modes of cache: Distill at run time the inactive instructions and place them in leakage mode Potential for performance degradation: Putting active instructions in leakage mode Hardware overhead: power and latency Previous approaches: Utilize architectural-level techniques Utilize hardware monitoring to manage the leakage modes of the cache Limitations:  Hardware complexity  Power savings could be moderate

5. Proposed approach Utilize compiler based technique Identify the last use of instructions and place them in leakage mode Special instructions are used to place cache lines into leakage modes Goals: Simplifies hardware support Improve power savings Two compiler-based strategies are studied: Conservative Optimistic Two leakage savings mechanisms are utilized State destroying and state preserving mode

6. Loop Body-I Loop Body-II Loop Body-III Compiler strategies Turn off instructions are applied at the loop level granularity Conservative: the lines for loop body-I can only be turned off when exiting loop III  Less effective when loop III encloses the majority of instructions in the code Optimistic: the lines for loop body-I can be turned off every time exiting loop I (Assume loop II take long time) When to turn off a cache line? Conservative strategy when sure its content is dead Optimistic strategy when incur a large gap in cycles

7. Examining various strategies ConservativeOptimistic State-destroying Strategy 1 Strategy 2 State-preserving Strategy 4 Strategy 3 Experimental results show that Strategy 3 is the most successful one Strategy 3 is competitive to other proposed schemes Strategies 1 and 2 are less successful due to the overhead of caches misses imposed by state destroying Hybrid strategy Policy: When exiting the loop: (1)if the loop will be visited again, put the cache lines in leakage mode (state preserving) (2)If the loop is dead, turn off cache lines (state-destroying) Hybrid strategy performed somewhat similar to strategy 3

8. Compiler optimizations Loop Distribution Fewer cache lines need to be activated at any given time Potential in reducing conflicts in L2 cache and improve performance  Possible destroy in data cache locality Loop Body-I Loop Body-II Loop Body-I Loop Body-II Header Body-I Body-II Header Body-I Body-II Header Loop distribution Loop fusion Loop Fusion Potential in enhancing data locality  Increase number of active lines at a given time Potential in reducing the time duration for the active lines

9. Compiler optimizations Impact of various optimizations on leakage energy on adi Experimental results show that Loop distribution is the most successful optimization in reducing leakage energy

10. Summary Proposed approach delivers competitive energy savings and energy-delay to other schemes Proposed approach delivers competitive energy savings and energy-delay to other schemes Applying loop optimizations improves energy savings Applying loop optimizations improves energy savings Hardware support is simple Hardware support is simple  Adding explicit turn-off instructions impose modifications into ISA