1. Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count- Directed Clustering Aiman El-Maleh and Saqib Khurshid King Fahd University of Petroleum & Minerals, Dept. of Computer Eng., Saudi Arabia Aiman El-Maleh and Saqib Khurshid King Fahd University of Petroleum & Minerals, Dept. of Computer Eng., Saudi Arabia

2. 2 OutlineOutline n Motivation n Test compaction techniques n Proposed Algorithm n Illustrative Example n Experimental results n Conclusions n Motivation n Test compaction techniques n Proposed Algorithm n Illustrative Example n Experimental results n Conclusions

3. 3 MotivationMotivation n Increasing complexity of systems-on-a-chip and its test data size increased cost of testing. n Cost of automatic test equipment increases with increase in speed, channel capacity, and memory. n Need for test data reduction is imperative Test compression Test compression Test compaction: Static and Dynamic Test compaction: Static and Dynamic n Static compaction techniques are preferred to dynamic compaction dynamic compaction is more time consuming dynamic compaction does not take advantage of random test pattern generation. static compaction is independent of ATPG (run ATPG in parallel to manage design complexity) n Increasing complexity of systems-on-a-chip and its test data size increased cost of testing. n Cost of automatic test equipment increases with increase in speed, channel capacity, and memory. n Need for test data reduction is imperative Test compression Test compression Test compaction: Static and Dynamic Test compaction: Static and Dynamic n Static compaction techniques are preferred to dynamic compaction dynamic compaction is more time consuming dynamic compaction does not take advantage of random test pattern generation. static compaction is independent of ATPG (run ATPG in parallel to manage design complexity)

4. 4 Static Test Compaction Techniques Static Compaction Algorithms for Combinational Circuits Redundant Vector Elimination Test Vector Addition & Removal Test Vector Modification Set Covering Test Vector Reordering Essential Fault Pruning Based on ATPG Essential Fault Pruning Based on ATPG Merging Based on Relaxation Based on Raising Test Vector Decomposition IFC CBC FCC

5. 5 Proposed Test Compaction Technique n Based on test vector decomposition and clustering. n Two vectors are clustered together if they are compatible. n Two test vectors are compatible if they do not have conflicting values in any bit position. n A test vector decomposed into a fault component contains only the assignments necessary for the detection of the fault. n Example T=10011101101 T=10011101101 Decomposed into T 1 for f 1 1xx1x10xx01 Decomposed into T 1 for f 1 1xx1x10xx01 Decomposed into T 2 for f 2 x0011x0xxxx Decomposed into T 2 for f 2 x0011x0xxxx n Based on test vector decomposition and clustering. n Two vectors are clustered together if they are compatible. n Two test vectors are compatible if they do not have conflicting values in any bit position. n A test vector decomposed into a fault component contains only the assignments necessary for the detection of the fault. n Example T=10011101101 T=10011101101 Decomposed into T 1 for f 1 1xx1x10xx01 Decomposed into T 1 for f 1 1xx1x10xx01 Decomposed into T 2 for f 2 x0011x0xxxx Decomposed into T 2 for f 2 x0011x0xxxx

6. 6 Proposed Test Compaction Technique n Fault detection count directed clustering (FCC). n Clustering in increasing order of faults detection count. n Clustering order gives more degree of freedom and results in better compaction. n A fault detected by N vectors has N test vector components All components will be checked for compatibility before creating a new cluster All components will be checked for compatibility before creating a new cluster n Fault detection count directed clustering (FCC). n Clustering in increasing order of faults detection count. n Clustering order gives more degree of freedom and results in better compaction. n A fault detected by N vectors has N test vector components All components will be checked for compatibility before creating a new cluster All components will be checked for compatibility before creating a new cluster

7. 7 FCC Algorithm n 1. Fault simulate T without fault dropping. 1.1 Record the number of test vectors detecting each fault. 1.1 Record the number of test vectors detecting each fault. n 2. Group the faults by their detection count. 2.1. Sort the faults in ascending order of their detection count. 2.1. Sort the faults in ascending order of their detection count. n 3. For every essential fault f that is detected by a test vector t: 3.1. Extract the atomic component c f from t. 3.1. Extract the atomic component c f from t. 3.2. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 3. 3.2. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 3. 3.3. Map c f to an existing compatibility set, if possible, and then go to Step 3. 3.3. Map c f to an existing compatibility set, if possible, and then go to Step 3. 3.4. Create a new compatibility set and map c f to it. 3.4. Create a new compatibility set and map c f to it. n 1. Fault simulate T without fault dropping. 1.1 Record the number of test vectors detecting each fault. 1.1 Record the number of test vectors detecting each fault. n 2. Group the faults by their detection count. 2.1. Sort the faults in ascending order of their detection count. 2.1. Sort the faults in ascending order of their detection count. n 3. For every essential fault f that is detected by a test vector t: 3.1. Extract the atomic component c f from t. 3.1. Extract the atomic component c f from t. 3.2. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 3. 3.2. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 3. 3.3. Map c f to an existing compatibility set, if possible, and then go to Step 3. 3.3. Map c f to an existing compatibility set, if possible, and then go to Step 3. 3.4. Create a new compatibility set and map c f to it. 3.4. Create a new compatibility set and map c f to it.

8. 8 FCC Algorithm n 4. Fault simulate all the compatibility sets and drop all the remaining faults that are detected. n 5. For each remaining undetected fault f that is detected by a set of test vector T’: 5.1. For every test vector t’, where t’ is a member of T’: 5.1. For every test vector t’, where t’ is a member of T’: 5.2. Extract the atomic component c f from t’. 5.2. Extract the atomic component c f from t’. 5.3. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 5. 5.3. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 5. 5.4. Map c f to an existing compatibility set, if possible, and then go to Step 5, otherwise go to Step 5.1. 5.4. Map c f to an existing compatibility set, if possible, and then go to Step 5, otherwise go to Step 5.1. n 4. Fault simulate all the compatibility sets and drop all the remaining faults that are detected. n 5. For each remaining undetected fault f that is detected by a set of test vector T’: 5.1. For every test vector t’, where t’ is a member of T’: 5.1. For every test vector t’, where t’ is a member of T’: 5.2. Extract the atomic component c f from t’. 5.2. Extract the atomic component c f from t’. 5.3. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 5. 5.3. If the number of compatibility sets is zero, create a new compatibility set, map c f to it, and then go to Step 5. 5.4. Map c f to an existing compatibility set, if possible, and then go to Step 5, otherwise go to Step 5.1. 5.4. Map c f to an existing compatibility set, if possible, and then go to Step 5, otherwise go to Step 5.1.

9. 9 FCC Algorithm n 6. Random fill test vectors of all the compatibility sets. n 7. Fault simulate all the compatibility sets and drop all detected faults. n 8. For each remaining undetected fault f detected by a set of test vector T’: 8.1. For every test vector t’, where t’ is a member of T’: 8.1. For every test vector t’, where t’ is a member of T’: 8.2. Extract the atomic component c f from t’. 8.2. Extract the atomic component c f from t’. 8.3. Map c f to an existing compatibility set, if possible, and then go to Step 8, otherwise go to Step 8.1. 8.3. Map c f to an existing compatibility set, if possible, and then go to Step 8, otherwise go to Step 8.1. 8.4. Create a new compatibility set and map c f to it. 8.4. Create a new compatibility set and map c f to it. n 6. Random fill test vectors of all the compatibility sets. n 7. Fault simulate all the compatibility sets and drop all detected faults. n 8. For each remaining undetected fault f detected by a set of test vector T’: 8.1. For every test vector t’, where t’ is a member of T’: 8.1. For every test vector t’, where t’ is a member of T’: 8.2. Extract the atomic component c f from t’. 8.2. Extract the atomic component c f from t’. 8.3. Map c f to an existing compatibility set, if possible, and then go to Step 8, otherwise go to Step 8.1. 8.3. Map c f to an existing compatibility set, if possible, and then go to Step 8, otherwise go to Step 8.1. 8.4. Create a new compatibility set and map c f to it. 8.4. Create a new compatibility set and map c f to it.

10. 10 Illustrative Example Test VectorFault Detected Fault Component v1v1 0000111110f1f1 0x0xx1xxx0 f4f4 00xx1xx1xx v2v2 1101101001f2f2 1xx1xx10x1 f5f5 xxxx10x0xx f6f6 1xx1x0x0x1 f8f8 x1xx1xx001 v3v3 1010111101f3f3 x0xxxx11x1 f5f5 xxxx1xx101 f6f6 1xxx11x10x f7f7 1x1x1xx10x v4v4 0011110101f3f3 x0x1x1xxx1 f4f4 00xxx1x1x1 f6f6 00xx11xx0x f7f7 xx1x1x0x0x f8f8 xxx11x0101 Fault Detection Count Faults1 f 1, f 2 2 f 3, f 4, f 5, f 7, f 8 3 f6f6f6f6

11. 11 Illustrative Example After mapping faults with detection count=1 After mapping faults with detection count=2 After mapping faults with detection count=3 After Merging Components After Random Filling ClusterFault Component Fault Component Fault Component Test Vector 1f1f1 0x0xx1xxx0f1f1 f1f1 000x11x1000001110100 f4f4 00xx1xx1xxf4f4 f6f6 00xx11xx0x 2f2f2 1xx1xx10x1f2f2 f2f2 10x1x110x11011011001 f3f3 x0x1x1xxx1f3f3 Test components for f 3 : {x0xxxx11x1, x0x1x1xxx1 } Test components for f 5 : {xxxx10x0xx, xxxx1xx101 }

12. 12 Iterative FCC n To increase level of compaction, FCC can be applied iteratively until no improvement is possible. n Apply FCC iteratively until the length of the test set cannot be reduced in the last six iterations (FCC6+). n Unspecified bits in the test set T are assigned random values before every call to the FCC algorithm. n To increase level of compaction, FCC can be applied iteratively until no improvement is possible. n Apply FCC iteratively until the length of the test set cannot be reduced in the last six iterations (FCC6+). n Unspecified bits in the test set T are assigned random values before every call to the FCC algorithm.

13. 13 Experimental results n Benchmark circuits ISCAS 85 and full-scanned versions of ISCAS 89 circuits ISCAS 85 and full-scanned versions of ISCAS 89 circuits n Test sets Generated by HITEC Generated by HITEC n Compared Techniques Reverse Order Fault Simulation (ROF): 20 iterations Reverse Order Fault Simulation (ROF): 20 iterations Random Merging (RM) Random Merging (RM) Independent Fault Clustering (IFC) Independent Fault Clustering (IFC) Iterative Independent Fault Clustering (IFC-ITR) Iterative Independent Fault Clustering (IFC-ITR) n Benchmark circuits ISCAS 85 and full-scanned versions of ISCAS 89 circuits ISCAS 85 and full-scanned versions of ISCAS 89 circuits n Test sets Generated by HITEC Generated by HITEC n Compared Techniques Reverse Order Fault Simulation (ROF): 20 iterations Reverse Order Fault Simulation (ROF): 20 iterations Random Merging (RM) Random Merging (RM) Independent Fault Clustering (IFC) Independent Fault Clustering (IFC) Iterative Independent Fault Clustering (IFC-ITR) Iterative Independent Fault Clustering (IFC-ITR)

14. 14 Test Compaction Results 475965132s4863 119145252359s5378 1382328191174s38584 1301878221472s38417 230248277704s3330 144181456657s15850 238252476633s13207 FCCRMROFOrig.Circuit 364252138s6669 170202375620s9234 An average compaction of 70% over the original test set An average compaction of 39% over ROF An average compaction of 21% over RM

15. 15 Comparison with IFC 3.95473.0250132s4863 11193.05120359s5378 154.0213847181481174s38584 225.951308381501472s38417 0.992303.05238704s3330 15.9714450.97142657s15850 10.0223834.06244633s13207 CPU#TVCPU#TV#TVCircuit 5.02367.9140138s6669 3.0417011.06182620s9234 IFC FCC Original An average compaction of 7% over IFC 51% less CPU time on average

16. 16 Comparison with Iterative IFC 6.963870.8842132s4863 13.99107109117359s5378 1735.171148217.081241174s38584 23371083775.061201472s38417 4.219230.02196704s3330 1365.98118374.95129657s15850 69.02234473.12238633s13207 CPU#TVCPU#TV#TVCircuit 12.0228175.0130138s6669 27.04139200.93155620s9234 ROF+IFC-ITR FCC6+ Original An average compaction of 8% over ROF+IFC-ITR 52% less CPU time on average

17. 17 Overall Test Compaction Comparison FCC6+ achieves an average compaction of 13.5% over FCC

18. 18 ConclusionsConclusions n Proposed a new test compaction technique for combinational circuits based on test vector clustering. n Test vectors are decomposed and clustered in an increasing order of fault detection count. n Higher level of compaction in a much more efficient CPU time than IFC. n An iterative application of the proposed technique has also shown significant increase in achieved level of test compaction. n Proposed a new test compaction technique for combinational circuits based on test vector clustering. n Test vectors are decomposed and clustered in an increasing order of fault detection count. n Higher level of compaction in a much more efficient CPU time than IFC. n An iterative application of the proposed technique has also shown significant increase in achieved level of test compaction.