1. מבנה המחשב - מבוא למחשבים ספרתיים Synchronous Circuits

2. Question 10.2 - Circuit Analysis Comb. Logic ANDD FF Q CLK

3. Question 10.2 - Circuit Analysis CLK case #1 – negative setup time t i-1 titi CiCi Logic Q D Not stableStable

4. Question 10.2 - Circuit Analysis CLK case #1 – negative setup time t i-1 titi CiCi Logic Q D Not stableStable

5. Question 10.2 - Circuit Analysis CLK case #2 – positive setup time t i-1 titi CiCi Logic Q D Not stableStable CiCi

6. Question 10.2 - Circuit Analysis CLK case #2 – positive setup time t i-1 titi CiCi Logic Q D Not stableStable CiCi

7. The Marvelous Toy

8. Toy Design Identifying system states Identifying state transitions and deciding on Moore or Mealy model Detailing the state machine transition and output functions The combinational circuits The Canonic circuit Clock rate calculation

9. Toy System States Only the three switching elements keep state. Each has a binary state: Left or Right We can model the state of every switch by a single bit. Convention: 0=Left, 1=Right The total number of states: 2 3 = 8

10. State Diagram 000

11. State Diagram 000 011 100 0/0 1/0 X is Left Z is Left Y is Left Enter from Left Out from Left Swap X Enter from Right Out from Left Swap Y & Z

12. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0

13. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0 110 001 0/0 1/1 Enter Right Out Right Swap Y&Z

14. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0 110 001 0/0 1/1 0/11/1

15. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0 101 110 001 0/0 1/1 0/11/1 0/1 1/1

16. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0 101 110 001 0/0 1/1 0/11/1 0/1 1/1 0/0 1/1

17. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0 101 110 001 0/0 1/1 0/11/1 0/1 1/1 0/0 1/1 0/0 1/1

18. State Diagram 000 011 100 0/0 1/0 111 010 0/0 1/0 101 110 001 0/0 1/1 0/11/1 0/1 1/1 0/0 1/1 0/0 1/1 0/0 1/1

19. Output Function Y=0 I=0 Y=0 I=1 Y=1 I=1 Y=1 I=0 X=0 Z=0 0010 X=0 Z=1 0110 X=1 Z=1 1111 X=1 Z=0 0010

20. Output Function Output = YI + XZ + ZI (This is λ) This circuit has 3 AND(2) in parallel, and then an OR(3) No NOT gates. Delay = D(AND)+2*D(OR) –Assuming we use OR(2) only

21. The Next State Function of X 000 011 100 0/0 1/0 111 010 0/0 1/0 101 110 001 0/0 1/1 0/11/1 0/1 1/1 0/0 1/1 0/0 1/1 0/0 1/1

22. Next State Function for X Y=0 I=0 Y=0 I=1 Y=1 I=1 Y=1 I=0 X=0 Z=0 1001 X=0 Z=1 1001 X=1 Z=1 0110 X=1 Z=0 0110

23. X Next State Function X = X’I’+XI (This is part of δ) This circuit has: –2 negations in parallel –2 AND(2) in parallel, –and then an OR(2) Delay = D(NOT)+D(AND)+D(OR)

24. The Canonic Circuit State Register Next State Circuit δ Output Circuit λ Input {0,1} Next State {0,1} 3 State {0,1} 3 Output {0,1}

25. Stripping away the Flip-Flops Next State Circuit δ Output Circuit λ Input {0,1} Next State {0,1} 3 State {0,1} 3 Output {0,1} D-portQ-port

26. Attaching Delay Next State Circuit pd(δ) Output Circuit pd(λ) Input {0,1} Next State {0,1} 3 State {0,1} 3 Output {0,1} D-portQ-port t pd pd(IN) setup(OUT) t su

27. Finding the Clock Rate Next State Circuit pd(δ) Output Circuit pd(λ) Input {0,1} Next State {0,1} 3 State {0,1} 3 Output {0,1} D-portQ-port t pd pd(IN) setup(OUT) t su

28. The Clock Rate We are done!