TopicF: Static and Dynamic Memories José Nelson Amaral

TopicF: Static and Dynamic Memories José Nelson Amaral
CMPUT329 - Fall 2003 TopicF: Static and Dynamic Memories José Nelson Amaral CMPUT Computer Organization and Architecture II

CMPUT 329 - Computer Organization and Architecture II
Reading Assignment Chapter 10 of Wakerly Sections 10.1, 10.2, 10.3, 10.4 CMPUT Computer Organization and Architecture II

Control Unit PcWrite ALUOp PcWriteCond PCSource IorD ALUSelA MemRead
TargetWrite 1 2 M u x MemWrite RegWrite Target IRWrite MemtoReg ALUSelB RegDst 32 4 Conc/ Shift left 2 32 26 PC M u x 1 M u x 1 I[25-21] Read address Read register 1 Instruction [31-26] I[20-16] Read data 1 Memory Read register 2 Zero Write address M u x 1 ALU result Instruction [25-0] Write register Read data 2 MemData M u x 1 2 3 ALU Write data Instruction register Write data 4 [15-11] Registers M u x 1 32 I[15-0] Sign ext. ALU control Shift left 2 16

EPROMs (Erasable Programmable Read Only Memories)
CS OE • A13 D0 D1 D7 27128 27256 A12 2764 A15 27512 8K  8 16K  8 32K  8 64K  8 A0-A15: Address Bus D0-D7: Data Bus CS: Chip Select OE: Output Enable CMPUT Computer Organization and Architecture II

Address Decoding on a Microprocessor System
• A0 A1 A14 O0 O1 O7 CS OE • D0 D1 D7 27256 A19 74x139 1G 1Y0 1Y1 1Y2 1Y3 1A 1B D0 D1 • D7 READ WRITE CMPUT Computer Organization and Architecture II

The 74x139 Decoder 1G_L 1A 1B 1Y0_L 1Y1_L 1Y2_L 1Y3_L 1Y0 1Y1 1Y2 1Y3 74x139 2Y0 2Y1 2Y2 2Y3 1G 1A 1B 2G 2A 2B 1 2 13 15 14 4 5 6 7 12 11 10 9 CMPUT Computer Organization and Architecture II

The 74x139 Decoder 1G_L 1A 1B 1Y0_L 1Y1_L 1Y2_L 1Y3_L CMPUT Computer Organization and Architecture II

The 74x139 Decoder 1G_L 1A 1B 1Y0_L 1Y1_L 1Y2_L 1Y3_L 1 CMPUT Computer Organization and Architecture II

The 74x139 Decoder 1Y0_L 1G_L 1Y1_L 1Y2_L 1A 1 1Y3_L 1B CMPUT Computer Organization and Architecture II

The 74x139 Decoder 1G_L 1A 1B 1Y0_L 1Y1_L 1Y2_L 1Y3_L CMPUT Computer Organization and Architecture II

The 74x139 Decoder 1Y0 1Y1 1Y2 1Y3 74x139 2Y0 2Y1 2Y2 2Y3 1G 1A 1B 2G 2A 2B 1 2 13 15 14 4 5 6 7 12 11 10 9 CMPUT Computer Organization and Architecture II

Address Decoding We want to design a microprocessor-based system with 128 Kbytes of EPROM using the EPROM chips that have an organization of 32K  8 bits. This particular microprocessor has a data bus that is 8-bit wide and an address bus that is 20-bits wide. The EPROM is to be mapped to the highest addresses of the memory address space. CMPUT Computer Organization and Architecture II

Address Decoding A memory address in this system has the following format: 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 1 32 Kbytes = 32  1024 = 25  210 = 215 bytes Thus we need 15 address lines to address 32 Kbytes. Therefore, the 32K highest addresses in this memory system have the following addresses. 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 CMPUT Computer Organization and Architecture II

Address Decoding The 64K highest addresses are the following addresses. 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 And the 128K highest addresses are: 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 CMPUT Computer Organization and Architecture II

Address Decoding Thus to verify if a memory access is to the EPROM region, we can just verify if the address lines A19, A18, and A17 are simultaneously 1: 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 A19 A18 A17 HIMEN_L CMPUT Computer Organization and Architecture II

Address Decoding To create a space of 128 Kbytes of EPROM with chips that have 32 Kbytes capacity, we will need four memory chips. How can we use the address lines to identify which memory chip is been accessed each time? CMPUT Computer Organization and Architecture II

Address Decoding The memory chip placed at the higher portion of the address space contains the memory addresses starting at: 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 F8000 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 And ending at: FFFFF CMPUT Computer Organization and Architecture II

Address Decoding 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 Bank 3 F8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFF 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 F0000 F7FFF Bank 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 E8000 EFFFF Bank 1 19 18 16 17 15 14 12 13 11 10 8 9 7 6 4 5 3 2 Bank E0000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 E7FFF CMPUT Computer Organization and Architecture II

Address Decoding 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bank 3 F8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFF 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bank 2 F0000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F7FFF 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bank 1 E8000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EFFFF 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bank E0000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 E7FFF CMPUT Computer Organization and Architecture II

Address Decoding on a Microprocessor System
27256 27256 27256 27256 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 • • • • • A14 D0 A14 D0 A14 D0 A14 D0 A14 O0 A14 O0 A14 O0 A14 O0 D1 D1 D1 D1 O1 O1 O1 O1 A19 • • • • A19 CS O7 O7 D7 CS D7 CS O7 O7 D7 CS D7 SE0000_L SE8000_L SF8000_L SF0000_L OE OE OE OE D0 D0 D1 D1 • D7 D7 READ A19 A18 A17 HIMEN_L 74x139 WRITE 1G 1Y0 1Y1 1Y2 1Y3 A15 A16 1A 1B

Types of Memories Read/Write Memory (RWM): we can store and retrieve data. Random Access Memory (RAM): the time required to read or write a bit of memory is independent of the bit’s location. Static Random Access Memory (SRAM): once a word is written to a location, it remains stored as long as power is applied to the chip, unless the location is written again. the data stored at each location must be refreshed periodically by reading it and then writing it back again, or else it disappears. Dynamic Random Access Memory (DRAM): CMPUT Computer Organization and Architecture II

Random Access Memories (RAMs)
A Random-Access Memory (RAM) is so called to contrast with its predecessor, the Serial-Access Memory. In a serial access memory, memory positions become available for reading on a sequential fashion. Therefore to read an specific memory position, the reader must wait a variable time delay for the memory position to became available. In principle, in a RAM, all positions of the memory can be read on a random fashion with approximately the same delay for all positions. However, modern RAMs allow burst accesses that favor sequential accesses (complete them in less time). CMPUT Computer Organization and Architecture II

Static-RAM Control Inputs
The outputs of memory chips are often connected to a three-state bus, a bus that can be driven by many devices. Therefore each memory chip should drive the bus only when commanded to do so by the control logic. Output Enable (OE): Enable the output into the data lines Chip Select (CS): Used in connection with OE to simplify the design of a multiple chip system. Write Enable (WE): When asserted, the data inputs are written to the selected memory location. The following control inputs are typically used to control a Static-RAM. CMPUT Computer Organization and Architecture II

A 2nb SRAM 2n  b SRAM Address inputs An-1 A0 A1 Data inputs DINb-1 DIN0 DIN1 DOUTb-1 DOUT0 DOUT1 Data outputs CS control inputs OE WE CMPUT Computer Organization and Architecture II

SRAMs (Static Random Access Memories)
IO0 IO1 IO7 OE CS1 • D0 D1 D7 2764 HM6264 WE CS2 HM62256 HM628128 HM628512 2764 2764 2764 A0 A0 A0 A0 A0 A0 A1 A1 A1 A1 A1 A1 • • • D0 D0 D0 A14 IO0 A16 IO0 A18 IO0 A14 D1 A16 D1 A18 D1 IO1 IO1 IO1 • WE • • WE CS1 WE D7 D7 D7 IO7 IO7 IO7 CS CS2 CS OE OE OE CMPUT Computer Organization and Architecture II

Accesses to SRAM Read An address is placed on the address inputs while CS and OE are asserted. The latch outputs for the selected memory locations are delivered to DOUT. Write An address is placed on the address inputs and a data word is placed on DIN; then CS and WE are asserted. The latches in the selected memory location open, and the input word is stored. CMPUT Computer Organization and Architecture II

1 2 3 4 5 6 7 3-to-8 decoder 1 A2 A1 A0 2 1 DIN3 DIN2 DIN1 DIN0 WE_L
1 2 3 4 5 6 7 DIN3 DIN2 DIN1 DIN0 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR 3-to-8 decoder IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR 1 A2 A1 A0 2 1 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WE_L WR_L CS_L IOE_L OE_L DOUT3 DOUT2 DOUT1 DOUT0

1 2 3 4 5 6 7 3-to-8 decoder 1 A2 A1 A0 2 1 DIN3 DIN3 DIN3 DIN3 WE_L
1 2 3 4 5 6 7 DIN3 DIN3 DIN3 DIN3 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR 3-to-8 decoder IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR 1 A2 A1 A0 2 1 IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WE_L WR_L CS_L IOE_L OE_L DOUT3 DOUT3 DOUT3 DOUT3

SRAM with Bi-directional Data Bus
microprocessor IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR WE_L WR_L CS_L IOE_L OE_L DIO3 DIO2 DIO1 DIO0 CMPUT Computer Organization and Architecture II

Internal Address Decoding
The SRAM shown in the previous slides had 3 address lines and stored 8 words, requiring a 3-to-8 internal decoder. Such a decoder requires eight AND gates, with three inputs each, and three inversors. Consider the HM SRAM that has 19 address lines and stores 512K words. What size internal decoder this chip requires? A 19-to-512K decoder with AND gates, each with 19 inputs? CMPUT Computer Organization and Architecture II

Internal Address Decoding
To avoid such a complexity in the decoding logic, all memories (EPROMs, SRAMs, and DRAMs) use two-dimensional decoding which reduces the decoder size to approximately the square root of the number of addresses. The memory cells are organized in a two-dimensional array. Some address lines are used to select a row and the others are used to select a column. The cell selected by the whole address is at the intersection of the row and the column. CMPUT Computer Organization and Architecture II

Static-RAM Read Timing
tAA (access time for address): how long it takes to get stable output after a change in address. tACS (access time for chip select): how long it takes to get stable output after CS is asserted. tOE (output enable time): how long it takes for the three-state output buffers to leave the high-impedance state when OE and CS are both asserted. tOZ (output-disable time): how long it takes for the three-state output buffers to enter high-impedance state after OE or CS are negated. tOH (output-hold time): how long the output data remains valid after a change to the address inputs. CMPUT Computer Organization and Architecture II

Static-RAM Read Timing
ADDR stable stable stable  tAA Max(tAA, tACS) CS_L tOH tACS OE_L tAA tOZ tOE tOZ tOE DOUT valid valid valid WE_L = HIGH CMPUT Computer Organization and Architecture II

Static-RAM Write Timing
tAS (address setup time before write): all address inputs must be stable at this time before both CS and WE are asserted. tAH(address hold time after write): all address inputs must be held stable until this time after CS or WE is negated. tCSW (chip-select setup before end of write): CS must be asserted at least this long before the end of the write cycle. tWP (write pulse width): WE must be asserted at least this long to reliably latch data into the selected cell. tDS (data setup time before end of write): All of the data inputs must be stable at this time before the write cycle ends. tDH (data hold time after the end of write): All data inputs must be held stable until this time after the write cycle ends. CMPUT Computer Organization and Architecture II

Dynamic Memory Cell An SRAM cell has a bi-stable latch that requires from four to six transistors to be built. To deliver the higher memory density required for computer systems, a single transistor memory cell was developed. 1-bit DRAM cell word line bit line CMPUT Computer Organization and Architecture II

Writing 1 in a Dynamic Memories
1-bit DRAM cell word line bit line To store a 1 in this cell, a HIGH voltage is placed on the bit line, causing the capacitor to charge through the on transistor. CMPUT Computer Organization and Architecture II

Writing 0 in a Dynamic Memories
1-bit DRAM cell word line bit line To store a 0 in this cell, a LOW voltage is placed on the bit line, causing the capacitor to discharge through the on transistor. CMPUT Computer Organization and Architecture II

Destructive Reads 1-bit DRAM cell word line bit line To read the DRAM cell, the bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. Depending on the charge in the capacitor, the precharged bit line is pulled slightly higher or lower. A sense amplifier detects this small change and recovers a 1 or a 0. CMPUT Computer Organization and Architecture II

Recovering from Destructive Reads
1-bit DRAM cell word line bit line The read operation discharges the capacitor. Therefore a read operation in a dynamic memory must be immediately followed by a write operation of the same value read to restore the capacitor charges. CMPUT Computer Organization and Architecture II

Forgetful Memories 1-bit DRAM cell word line bit line The problem with this cell is that it is not bi-stable: only the state 0 can be kept indefinitely, when the cell is in state 1, the charge stored in the capacitor slowly dissipates and the data is lost. CMPUT Computer Organization and Architecture II

Refreshing the Memory Vcap 0V HIGH LOW VCC time 0 stored 1 written refreshes The solution is to periodically refresh the memory cells by reading and writing back each one of them. CMPUT Computer Organization and Architecture II

Refreshing Frequency Each dynamic RAM cell must be refreshed at about
every 4 miliseconds. Some commercial DRAMs contain 256 megabits. If we would refresh each cell every 4 miliseconds we would have to perform a refresh operation every: There would be no time for regular memory accesses!! How do we solve this problem? CMPUT Computer Organization and Architecture II

Refreshing Memory The DRAMs are organized in two dimensional arrays, and a single refreshing operation can refresh an entire row at a time. Newer DRAMs have 4096 rows, but only need to be refreshed every 64 miliseconds. Therefore they require one refresh operation about every 15.6 second. A refresh operation typically takes 100 nanoseconds. Therefore the memory is available for regular accesses more than 99% of the time. CMPUT Computer Organization and Architecture II

Internal Structure of a 64K  1 DRAM
Row decoder 256  256 array row address column address A0-A7 control Column latches, multiplexers, and demultiplexers RAS_L CAS_L WE_L latch, mux, and dmux control DOUT DIN CMPUT Computer Organization and Architecture II

Read Cycle on an Asynchronous DRAM
Step 1: Apply row address 1 Step 8: RAS and CAS return to high 8 Step 2: RAS go from high to low and remain low 2 Step 5: CAS goes from high to low and remain low 5 Step 3: Apply column address 3 Step 4: WE must be high 4 Step 6: OE goes low 6 Step 7: Data appears 7 Read Cycle on an Asynchronous DRAM

Write Cycle on an Asynchronous DRAM

Improved DRAMs Central Idea: Each read to a DRAM actually reads a complete row of bits or word line from the DRAM core into an array of sense amps. A traditional asynchronous DRAM interface then selects a small number of these bits to be delivered to the cache/microprocessor. All the other bits already extracted from the DRAM cells into the sense amps are wasted. CMPUT Computer Organization and Architecture II

Fast Page Mode DRAMs In a DRAM with Fast Page Mode, a page is defined as all memory addresses that have the same row address. To read in fast page mode, all the steps from 1 to 7 of a standard read cycle are performed. Then OE and CAS are switched high, but RAS remains low. Then the steps 3 to 7 (providing a new column address, asserting CAS and OE) are performed for each new memory location to be read. CMPUT Computer Organization and Architecture II

A Fast Page Mode Read Cycle on an Asynchronous DRAM

Enhanced Data Output RAMs (EDO-RAM)
The process to read multiple locations in an EDO-RAM is very similar to the Fast Page Mode. The difference is that the output drivers are not disabled when CAS goes high. This distintion allows the data from the current read cycle to be present at the outputs while the next cycle begins. As a result, faster read cycle times are allowed. CMPUT Computer Organization and Architecture II

An Enhanced Data Output Read Cycle on an Asynchronous DRAM

Synchronous DRAMs (SDRAM)
A Synchronous DRAM (SDRAM) has a clock input. It operates in a similar fashion as the fast page mode and EDO DRAM. However the consecutive data is output synchronously on the falling/rising edge of the clock, instead of on command by CAS. How many data elements will be output (the length of the burst) is programmable up to the maximum size of the row. The clock in an SDRAM typically runs one order of magnitude faster than the access time for individual accesses. CMPUT Computer Organization and Architecture II

SDRAM Burst Read Cycle CMPUT Computer Organization and Architecture II

DDR SDRAM A Double Data Rate (DDR) SDRAM is an SDRAM that allows data transfers both on the rising and falling edge of the clock. Thus the effective data transfer rate of a DDR SDRAM is two times the data transfer rate of a standard SDRAM with the same clock frequency. CMPUT Computer Organization and Architecture II

The Rambus DRAM (RDRAM)
Multiple memory arrays (banks) Rambus DRAMs are synchronous and transfer data on both edges of the clock. CMPUT Computer Organization and Architecture II

SDRAM Memory Systems Complex circuits for RAS/CAS/OE. Each DIMM is connected in parallel with the memory controller. (DIMM = Dual In-line Memory Module) Often requires buffering. Needs the whole clock cycle to establish valid data. Making the bus wider is mechanically complicated. CMPUT Computer Organization and Architecture II

RDRAM Memory Systems CMPUT Computer Organization and Architecture II

Internal RDRAM Organization
CMPUT Computer Organization and Architecture II

SDRAM Protocol Notice the different delays between RAS and the first data in the data bus for read and write operations. This creates bubbles when transiting from write to read. Write Read CMPUT Computer Organization and Architecture II

RDRAM Protocol CMPUT Computer Organization and Architecture II

Bank Conflicts If two consecutive memory accesses are accessing the same memory bank, there will be a delay, or a bubble, in the response. This delay happens because a memory device needs time to “recover” after it completes a memory access. Thus the more banks a memory system has, the less likely it will be to have delays caused by memory bank conflicts. CMPUT Computer Organization and Architecture II

SDRAM Bank Conflicts CMPUT Computer Organization and Architecture II

RDRAM Banks  SDRAM Banks

Dual In-line Memory Module (DIMM)

Rambus In-line Memory Module (RIMM)

A picture of RIMMs CMPUT Computer Organization and Architecture II

Further Reading To learn more about the differences between SDRAM systems and Rambus DRAM systems for personal computers, visit these websites: Crisp, Richard, “Direct Rambus Technology: The New Main Memory Standard,” IEEE Micro, 17(6): 18-28, Nov/Dec, 1997. CMPUT Computer Organization and Architecture II

TopicF: Static and Dynamic Memories José Nelson Amaral

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