1. Prith Banerjee ECE C03 Advanced Digital Design Spring 1998
Lecture 11 Memory Design
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 11

2. Outline Random Access Memories (RAMS) Static RAMs Dynamic RAMS
Memory Organizations
Read-Only Memories (ROMS)
READING: Katz 7.6, 4.2.5
ECE C03 Lecture 11

3. Memory Need method for storing large amounts of data
Computer programs, data, pictures, etc.
RAM: Random Access Memory, Read/Write
ROM: Read-only Memory
64x8 RAM
A D7
A D6
A D5
A D4 D3 D2 D1
Write D0
ECE C03 Lecture 11

4. 8x4 RAM Address Data A2 A1 A0 Out3 Out2 Out1 Out0 000 001 010 011 100
101
110
111 A2 A1 A0
ECE C03 Lecture 11
Out Out Out Out0

5. 8x4 RAM In3 In2 In1 In0 Write A2 A1 A0 Out3 Out2 Out1 Out0 000 001 010
011
100
101
110
111
3:8
Decoder
Enable
S2 S1 S0 A2 A1 A0
ECE C03 Lecture 11
Out Out Out Out0

6. RAM Cell Requirements: Store one bit of data
Change data based on input when row is selected
Input S Q R
Row Select
ECE C03 Lecture 11

7. Static Random Access Memories
Transistor efficient methods for implementing storage elements
Small RAM: 256 words by 4-bit
Large RAM: 4 million words by 1-bit
We will discuss a 1024 x 4 organization
Data
Data j j
Word Enable i
Words = Rows
Static RAM Cell
Static RAM Cell
Static RAM Cell
ECE C03 Lecture 11
Columns = Bits (Double Rail Encoded)

8. Static RAM Organization
1024 x 4 SRAM CS
Chip Select Line (active lo)
Write Enable Line (active lo)
10 Address Lines
4 Bidirectional Data Lines WE A9 A8 A7
IO3 A6
IO2 A5
IO1 A4
IO0 A3 A2 A1 A0
ECE C03 Lecture 11

9. RAM Organization
Long thin layouts are not the best organization for a RAM A9
Address
Buffers A8
Storage Matrix
Storage Array
64 x 64
Square
Array
Some Addr
bits select
row A7 A6 A5
64 x 16
64 x 16
64 x 16
64 x 16
Row A4
Decoders A3
Address
Buffers
Some Addr
bits select
within row A2
Amplifers &
Mux/Demux
Sense Amplifiers A1
Column A0
Decoders CS
Data Buffers WE
ECE C03 Lecture 11
I/O0
I/O1
I/O2
I/O3

10. RAM Timing Simplified Read Timing Simplified Write Timing
ECE C03 Lecture 11

11. Dynamic Random Access Memories
1 Transistor (+ capacitor) memory element
Read: Assert Word Line, Sense Bit Line
Write: Drive Bit Line, Assert Word Line
Destructive Read-Out
Need for Refresh Cycles: storage decay in ms
Internal circuits read word and write back
Word Line
Bit Line
ECE C03 Lecture 11

12. DRAM Organization Long rows to simplify refresh
Two new signals: RAS, CAS
Row Address Strobe
Column Address Strobe
replace Chip Select
Storage Matrix
Row
Decoders
64 x 64
Row Address
Column Address &
Control Signals
A11
Column Latches,
Multiplexers/Demultiplexers A0
Control
RAS
Logic
CAS WE
DOUT
DIN
ECE C03 Lecture 11

13. RAM Addressing Even to read 1 bit, an entire 64-bit row is read!
Separate addressing into two cycles: Row Address, Column Address
Saves on package pins, speeds RAM access for sequential bits!
Address
Row Address
Col Address
RAS
Read Cycle
CAS
Dout
Valid
Read Row
Row Address Latched
Read Bit Within Row
Column Address Latched
Tri-state
Outputs
ECE C03 Lecture 11

14. RAM Write Timing (1) Latch Row Address Read Row (2) WE low
Col Address
RAS
(1) Latch Row Address
Read Row
CAS WE
(2) WE low
Din
Valid
(3) CAS low: replace data bit
(4) RAS high: write back the modified row
(5) CAS high to complete the memory cycle
ECE C03 Lecture 11

15. DRAM Refresh Refresh Frequency:
4096 word RAM -- refresh each word once every 4 ms
Assume 120ns memory access cycle
This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!
But RAM is really organized into 64 rows
This is one refresh cycle every 62.5 µs (1 in 500 DRAM accesses)
Large capacity DRAMs have 256 rows, refresh once every 16 µs
RAS-only Refresh (RAS cycling, no CAS cycling)
External controller remembers last refreshed row
Some memory chips maintain refresh row pointer
CAS before RAS refresh: if CAS goes low before RAS, then refresh
ECE C03 Lecture 11

16. Variations of DRAMs Page Mode DRAM:
read/write bit within last accessed row without RAS cycle
RAS, CAS, CAS, . . ., CAS, RAS, CAS, ...
New column address for each CAS cycle
Static Column DRAM:
like page mode, except address bit changes signal new cycles
rather than CAS cycling
on writes, deselect chip or CAS while address lines are changing
Nibble Mode DRAM:
like page mode, except that CAS cycling implies next column
address in sequence -- no need to specify column address after
first CAS
Works for 4 bits at a time (hence "nibble")
RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .
ECE C03 Lecture 11

17. RAM Expansion Implement a big RAM from multiple small RAMS
Address
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ECE C03 Lecture 11

18. RAM Expansion (cont) Build a 16x16 RAM from 16x4 RAMs 16x4 RAM A3 Din
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
ECE C03 Lecture 11

19. RAM Expansion (cont) Build a 32x16 RAM from 16x4 RAMs 16x4 RAM A3 Din
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
16x4 RAM
A Din A2
A Dout A0
Write
ECE C03 Lecture 11

20. Read-Only Memories
This is another class of memory, which is read only, cannot write.
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V
+5V
+5V
+5V n
2 -1 i
Word Line 0011
Dec j
Word Line 1010
Bit Lines
n-1
Address
ECE C03 Lecture 11
Internal Organization

21. ROMs vs PLAs Not unlike a PLA structure with a fully decoded
AND array!
ROM vs. PLA:
ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
ECE C03 Lecture 11

22. Read-Only Memories 2764 EPROM 8K x 8 16K x 16 Subsystem U3 U2 U1 U0+
2764 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 O0 O1 O2 O3 O4 O5 O6 O7 OE CS
PGM
VPP
A10
A11
A12 A5 A6 A7 A8 A9 O0 O1 O2 O3 O4 O5 O6 O7 OE CS
PGM
VPP
A10
A11
A12 +
A13
/OE
A12:A0 U3 U2
D15:D8
D7:D0 U1 U0
16K x 16
Subsystem
ECE C03 Lecture 11

23. Implementing Logic with ROMs
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C' by
ECE C03 Lecture 11

24. Summary Random Access Memories (RAMS) Static RAMs Dynamic RAMS
Memory Organizations
Read-Only Memories (ROMS)
NEXT LECTURE: Finite State Machine Design
READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2
ECE C03 Lecture 11