1. Chapter 6 : Channel Refinement

2. SystemC Communication Refinement Vital part of overall system refinement: Add more details  To gain more precise analysis results  Towards the final system implementation (e.g. HW synthesis) Map abstract communication to actual implementation for  More structural accuracy  More pin accuracy  More timing accuracy  More clock-cycle accuracy  More functional accuracy  More data organization accuracy  More communication protocol accuracy

3. Refinement Design Flow 1. Select and replace Select a refined implementation for a component (channel or module). Replace original  channel/module with the refined version. 2. Insert adapters and/or converters  To re-establish connections insert appropriate adapters and/or converters 3. Re-run simulation and analyze functionality/performance  Check for correct functionality of refined system (the behavior may have changed!) 4. (Optional) Ungroup hierarchy  Flatten wrapped channels to make adapters visible outside 5. (Optional) Wrap channels and adapters/converters  Create new hierarchy to encapsule instances 6. (Optional) Protocol inlining  Merge channels/modules with their adapters/converters 7. (Optional) Restructure control flow  Make inherent parallelism more explicit (see example later) 8. (Optional) Analyze implementation  E.g. run synthesis and back-annotate area/timing/power results into model

4. Design Example Goal: Refine a SystemC model with a synthesizable HW implementation  Original design is constructed with sc_fifo  Replace sc_fifo with hw_fifo

5. Design Example (cont.) Select and replace Insert adapters  A1 : hw_fifo write adapter  A2 : hw_fifo read adapter

6. SystemC HW-HW Comm. Refinement Adapter Adapter A1 : w_adapter  Needs to implement the all the virtual function and below is an example  Connects to the pin-level ports of hw_fifo class w_adapter : public sc_module, public sc_fifo_out_if { public: sc_in_clk clock; sc_out data_port; sc_out valid_port; sc_in ready_port; // blocking write void w_adapter::write(const int& data) { while( !(ready_port.read()) ) wait(clock.posedge_event()); data_port = data; valid_port = true; wait( clock.posedge_event()); valid_port = false; wait( clock.posedge_event()); } // constructor w_adapter(sc_module_name name) : sc_module(name){ valid.initialize(false); } };