1. 1 Performed by: Lin Ilia Khinich Fanny Instructor: Fiksman Eugene המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Mid Stage Presentation Virtex II Pro FPGA Dynamic Reconfiguration Spring semester 2005

3. Abstract Partial reconfiguration involves defining distinct portions of an FPGA design to be reconfigured while the rest of the device remains in active operation. These portions are referred to as reconfigurable modules. Active partial reconfiguration is done when the device is active.

4. Virtex II Pro Architecture Configuration Data Bits that directly define the state of programmable logic. These are written to a Virtex-II Pro device in a configuration bitstream, and read as readback data from a Virtex-II Pro device. Configuration File The internally stored file that controls the FPGA so that it performs the desired logic function. Also, the act of loading an FPGA with that file.

5. Configuration of Virtex II Pro Configuration Frame The configuration bits in a Virtex-II Pro device are organized in columns. The smallest number of bits that can be read or written through the configuration interfaces is one frame. Configuration Interface A logical interface on the Virtex-II Pro device through which configuration commands and data can be read and written. A interface consists of one or more physical device pins.

6. Partial Reconfiguration New data is loaded to reconfigure a specific area of a device, while the rest of the device is still in operation. Active partial reconfiguration of Virtex devices is accomplished in either slave SelectMAP mode or Boundary Scan (JTAG) mode. Is useful for applications that require the loading of different designs into the same area of the device or the flexibility to change portions of a design.

7. Modular Design Modular Design allows to independently work on different pieces, or modules of a design and later merge these modules into one FPGA design. Modular Design is best used for large designs that can easily be partitioned into self-contained modules.

8. Module-based Partial Reconfiguration Module-based Partial Reconfiguration is used when communication is needed between modules. For modules that communicate with each other, a special bus macro allows signals to cross over a Partial Reconfiguration boundary.

9. System Architecture PLB OPB Controller Interface PPC405BRAM ICAP UART Reconfigurable Logic RAM Microblaze CPU Interface ICAP Interface

10. ICAP Interface The fundamental module used to perform in-circuit reconfiguration of Virtex-II Pro devices. A direct access to the configuration registers as well as a configuration data transfer using the SelectMAP" protocol.

11. Design Flows HW Block Diagram HW Description Synthesize P&R BIT File/ Download Base HW Flow SW Flow Chart Create SW Source Compile Simulate ELF File/ Download SW Flow ISE Design Debug (HW and SW) DATA2BRAM EDK HW Block Diagram HW Description Synthesize P&R BIT File/ On Chip Memory Partial HW Flow

12. Physical Limitations For current FPGA devices, data is loaded on a column-basis, with the smallest load unit being a configuration bitstream "frame," which varies in size based on the target device.

13. Physical Limitations 1.The reconfigurable module height is always the full height of the device. 2.The Reconfigurable module width ranges from a minimum of four slices to a maximum of the full- device width, in four-slice increments. 3.Horizontal placement must always be on a four-slice boundary; the leftmost placement being x = 0, 4, 8, … 4.All logic resources encompassed by the width of the module are considered part of the reconfigurable module's bitstream "frame." This includes slices, TBUFs, block RAMs, multipliers, IOBs, and most importantly, all routing resources.

14. Physical Limitations 5. Clocking logic (BUFGMUX, CLKIOBs) is always separate from the reconfigurable module. Clocks have separate bitstream frames. 6. IOBs immediately above the top edge and below the bottom edge of a reconfigurable module are part of the specific reconfigurable module's resources. 7. If a reconfigurable module occupies either the leftmost or rightmost slice column, all IOBs on the specific edge are part of the specific reconfigurable modules resources.

15. The way to the goal The considered physical limitations are applied on the bitstream compilation stage. The number of reconfigurable modules should be minimized (ideally, just a single reconfigurable module, if possible), but is only limited by the number of slice columns divided by four. The limitations are controlled by modification of script, generated on the netlist creation stage.

16. What was already done ? A lot of theoretical studies. Experiments with different design flows. Experiments with development tools. Block diagram of complete design.

17. Next Steps 1.Deciding of reconfigurable logic functionality. 2.Details of the controller implementation. Implementation beginning. 3.Building a working hardware example. 4.Documentation for the performed steps.