1. Status – Week 206 Victor Moya

2. Summary Fetch Cache. Fetch Cache. ColorCache. ColorCache. ColorWrite. ColorWrite. Next week. Next week.

3. Fetch Cache Interface: Interface: Fetch. Fetch. Reserves a cache line and requests the data to memory. Reserves a cache line and requests the data to memory. Writes the line data to memory if there was modified data. Writes the line data to memory if there was modified data. Allocate. Allocate. Reserves a line. Reserves a line. Writes the line data to memory if there was modified data. Writes the line data to memory if there was modified data. Sets write mask mode (for memory transactions). Sets write mask mode (for memory transactions).

4. Fetch Cache Interface: Interface: Read Read Reads an amount of data from a fetched line. Reads an amount of data from a fetched line. Write Write Writes an amount of data to a fetched/allocated line. Writes an amount of data to a fetched/allocated line. Unreserves the line. Unreserves the line. Write Masked. Write Masked. Writes using a write mask an amount of data to a fetched/allocated line. Writes using a write mask an amount of data to a fetched/allocated line. Unreserves the line. Unreserves the line. Unreserve: Unreserve: Unreserves a line (when no write is performed after fetch/allocate). Unreserves a line (when no write is performed after fetch/allocate).

5. Fetch Cache Interface: Interface: Flush: Flush: Flush mode. Flush mode. Adds modified lines to the memory request queue. Adds modified lines to the memory request queue. To be called once per cycle when flushing the cache. To be called once per cycle when flushing the cache. ProcessMemoryTransaction: ProcessMemoryTransaction: Receives and processes memory transactions (MT_READ_DATA). Receives and processes memory transactions (MT_READ_DATA). Is called only when there are new transactions. Is called only when there are new transactions. Update: Update: Generates new memory transactions. Generates new memory transactions. Updates fetch cache timing (buses, ports) and memory request queue. Updates fetch cache timing (buses, ports) and memory request queue. To be called ocne per cycle. To be called ocne per cycle.

6. Fetch Cache Suggested modifications: Suggested modifications: Flush: Flush: Just sets a flag => flushMode. Just sets a flag => flushMode. The flush tasks are done at update. The flush tasks are done at update. Update: Update: Rename to clock (as that is what is …). Rename to clock (as that is what is …). Add another function to retrieve the generated memory transactions rather than using update/clock to return them. Add another function to retrieve the generated memory transactions rather than using update/clock to return them.

7. Fetch Cache Problems: Problems: Memory bus width vs Cache port width. Memory bus width vs Cache port width. portWidth < memBusWidth makes sense? portWidth < memBusWidth makes sense? Add buffers to reduce contention. Add buffers to reduce contention. Mixed write and write masked calls are not supported. Mixed write and write masked calls are not supported. Write uses ‘fast’ 4 byte copy. Write uses ‘fast’ 4 byte copy. Write mask uses slow 1 byte copy and set mask. Write mask uses slow 1 byte copy and set mask.

8. Fetch Cache Problems: Problems: Makes sense to have timing at fetch cache will not being a Box? Makes sense to have timing at fetch cache will not being a Box?

9. ColorCache Not a box (yet). Not a box (yet). Now is just a wrapper for Fetch Cache: Now is just a wrapper for Fetch Cache: Just hides size parameter of the read/write operations. Just hides size parameter of the read/write operations.

10. ColorCache To be added: To be added: Fast clear. Fast clear. State block memory marks color blocks/lines as cleared (or compressed/uncompressed). State block memory marks color blocks/lines as cleared (or compressed/uncompressed). Intercepts memory transactions for cleared lines. Intercepts memory transactions for cleared lines. Color compression. Color compression. Intercepts memory transactions. Intercepts memory transactions. Compress (write) or decompress (read) color data. Compress (write) or decompress (read) color data. Write only mode (write buffer, masked memory transactions): Write only mode (write buffer, masked memory transactions): –Requires read of uncompressed lines/blocks before recompression/write.

11. ColorCache Implement as a box: Implement as a box: Current interface is converted to signals: Current interface is converted to signals: Command Signal: Command Signal: –Flush/Reset. Allocation Signal: Allocation Signal: –Fetch/Allocate/Unreserve. Write Signal: Write Signal: –Write/Write Masked. Read Signal: Read Signal: –Read. Memory Input Signal: Memory Input Signal: –ProcessMemoryTransaction MemoryOutputSignal: MemoryOutputSignal: –Update.

12. ColorCache Implement as a box: Implement as a box: Update becomes clock(). Update becomes clock().

13. ColorCache Problems with box model: Problems with box model: Half cycle latencies are not supported. Half cycle latencies are not supported. Latencies larger than 1 for fetch/allocate can generate problems. Latencies larger than 1 for fetch/allocate can generate problems. Fetch/Allocate are not in order: Fetch/Allocate are not in order: –required for avoiding inanition!!!) –Fetch/Allocate success is reported 1+ cycle too late. –Could help hide conflict misses. Force in-order fetch/allocate: Force in-order fetch/allocate: –Any fetch/allocate request after a fetch/allocate that failed is rejected until the first one can be done. –Serializes. Adds latency. Add a priority system. Add a priority system.

14. fetchA not accepted fetchA fetchB not accepted fetchA fetchB accepted fetchB accepted fetchB fetchCfetchA not accepted fetchA not accepted fetchA fetchC accepted fetchC

15. ColorCache Case analysis: Case analysis: Fetch A and Fetch B different: Fetch A and Fetch B different: Fetch A and Fetch B are the same line: Fetch A and Fetch B are the same line: –Both must wait. –Order is not important. Fetch A and Fetch B are not the same line: Fetch A and Fetch B are not the same line: –Fetch A and Fetch B go to the same cache line (aliasing): If cache line is reserved for both, both wait. If cache line is reserved for both, both wait. If cache line is unreserved for B A will have to wait even further. Worst case in example. If cache line is unreserved for B A will have to wait even further. Worst case in example. Order is not important. Order is not important. –Fetch A and Fetch B go to different lines: A waits, B continues. A waits, B continues. Could help hide latency until line for A is available. Could help hide latency until line for A is available. Order is not important. Order is not important.

16. ColorCache Case analysis: Case analysis: Fetch A and Fetch B are equal: Fetch A and Fetch B are equal: Fetch A and Fetch are from different triangles. Fetch A and Fetch are from different triangles. Order important!!! Order important!!! If latency is larger than 2 then more fetched addresses must be taking into account!!!! If latency is larger than 2 then more fetched addresses must be taking into account!!!!

17. ColorWrite Tested a simple blend mode. Tested a simple blend mode.

18. Next Week Z Test box. Z Test box. Fast Color Clear (without compression). Fast Color Clear (without compression). Trace statistics. Trace statistics.