1. 8/17/06 ELEC 5970-003/6970-003 Lecture 1 1 ELEC 5970-003/6970-003 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Introduction Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 8/17/06ELEC 5970-003/6970-003 Lecture 12 Course Objective Low-power is a current need in VLSI design. Low-power is a current need in VLSI design. Learn basic ideas, concepts and methods. Learn basic ideas, concepts and methods. Gain hands-on experience. Gain hands-on experience.

3. 8/17/06ELEC 5970-003/6970-003 Lecture 13 Student Evaluation Homework (30%) ~ Four Homework (30%) ~ Four Class Project (30%) Class Project (30%) Student presentation (10%) Student presentation (10%) Final Exam (30%) Final Exam (30%)

4. 8/17/06ELEC 5970-003/6970-003 Lecture 14 Introduction Why is it a concern? Power Consumption of VLSI Chips

5. 8/17/06ELEC 5970-003/6970-003 Lecture 15 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

6. 8/17/06ELEC 5970-003/6970-003 Lecture 16 VLSI Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

7. 8/17/06ELEC 5970-003/6970-003 Lecture 17 SIA Roadmap for Processors (1999) Year199920022005200820112014 Feature size (nm) 180130100705035 Logic transistors/cm 2 6.2M18M39M84M180M390M Clock (GHz) 1.252.13.56.010.016.9 Chip size (mm 2 ) 340430520620750900 Power supply (V) 1.81.51.20.90.60.5 High-perf. Power (W) 90130160170175183 Source: http://www.semichips.orghttp://www.semichips.org

8. 8/17/06ELEC 5970-003/6970-003 Lecture 18 Defining Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. General topics General topics Algorithms and architectures Algorithms and architectures High-level and software techniques High-level and software techniques Gate and circuit-level methods Gate and circuit-level methods Power estimation techniques Power estimation techniques Test power Test power

9. 8/17/06ELEC 5970-003/6970-003 Lecture 19 Specific Topics in Low-Power Power dissipation in CMOS circuits Power dissipation in CMOS circuits Device technology Device technology Low-power CMOS technologies Low-power CMOS technologies Energy recovery methods Energy recovery methods Circuit and gate level methods Circuit and gate level methods Logic synthesis Logic synthesis Dynamic power reduction techniques Dynamic power reduction techniques Leakage power reduction Leakage power reduction System level methods System level methods Microprocessors Microprocessors Arithmetic circuits Arithmetic circuits Low power memory technology Low power memory technology Test Power Test Power Power estimation Power estimation

10. 8/17/06ELEC 5970-003/6970-003 Lecture 110 Power in a CMOS Gate V DD i DD (t) Ground

11. 8/17/06ELEC 5970-003/6970-003 Lecture 111 Power Dissipation in CMOS Logic (0.25 µ ) %75%5%20 P total (0 → 1) = C L V DD 2 + t sc V DD I peak + V DD I leakage CLCL

12. 8/17/06ELEC 5970-003/6970-003 Lecture 112 Power and Energy Instantaneous power (Watts) Instantaneous power (Watts) P (t ) = i DD t ) V DD P (t ) = i DD (t ) V DD Peak power (Watts) Peak power (Watts) P peak = Max {P (t )} P peak = Max {P (t )} Average power (Watts) Average power (Watts) P av = [ ∫ 0 T P (t ) dt ] / T P av = [ ∫ 0 T P (t ) dt ] / T Energy (Joules) Energy (Joules) E = ∫ 0 T P (t ) dt E = ∫ 0 T P (t ) dt

13. 8/17/06ELEC 5970-003/6970-003 Lecture 113 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage

14. 8/17/06ELEC 5970-003/6970-003 Lecture 114 Power of a Transition V DD Ground C R R Power = CV DD 2 /2

15. 8/17/06ELEC 5970-003/6970-003 Lecture 115 Logic Activity and Glitches 4 5 7 6 1 2 3 d=2 d=1

16. 8/17/06ELEC 5970-003/6970-003 Lecture 116 Low-Power Design Techniques  Circuit and gate level methods  Reduced supply voltage  Adiabatic switching and charge recovery  Logic design for reduced activity  Reduced Glitches  Transistor sizing  Pass-transistor logic  Pseudo-nMOS logic  Multi-threshold gates

17. 8/17/06ELEC 5970-003/6970-003 Lecture 117 Low-Power Design Techniques Functional and architectural methods Functional and architectural methods Clock suppression Clock suppression Clock frequency reduction Clock frequency reduction Supply voltage reduction Supply voltage reduction Power down Power down Algorithmic and Software methods Algorithmic and Software methods

18. 8/17/06ELEC 5970-003/6970-003 Lecture 118 Test Power Power grid on a VLSI chip is designed for certain current capacity during functional operation: Power grid on a VLSI chip is designed for certain current capacity during functional operation: Average current → heat dissipation Average current → heat dissipation Peak current → noise, ground bounce Peak current → noise, ground bounce Problem – Tests like scan or BIST are nonfunctional and may cause higher than the functional circuit activity; a functionally good chip can fail the test. Problem – Tests like scan or BIST are nonfunctional and may cause higher than the functional circuit activity; a functionally good chip can fail the test.

19. 8/17/06ELEC 5970-003/6970-003 Lecture 119 Power Estimation Methods Spice: Accurate but expensive Spice: Accurate but expensive Logic-level Logic-level Event-driven simulation Event-driven simulation Statistical Statistical Probabilistic Probabilistic High-level: Hierarchical High-level: Hierarchical

20. 8/17/06ELEC 5970-003/6970-003 Lecture 120 Books on Low-Power Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, 1997. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, 1997. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, 1999. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, 1999. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997. W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997.

21. 8/17/06ELEC 5970-003/6970-003 Lecture 121 Books on Low-Power Design (2) N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley-Interscience, 2000. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley-Interscience, 2000. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, 1995. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, 1995. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, 2001. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, 2001. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, 1998. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, 1998. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004.

22. 8/17/06ELEC 5970-003/6970-003 Lecture 122 Other Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, 2001. A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, 2001. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts, Addison-Wesley, 2005. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts, Addison-Wesley, 2005. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004.