1. Ping Project Justin Knowles Kurt Lorhammer Brian Smith Andrew Tank ECEN 4610

2. Ping Project – What the Company Wants To design a device that both measures and communicates various aspects of the golf swing The device be portable, must interface with a laptop, and cannot interfere with the golf swing in any way It must also be lightweight and self-sufficient

3. Our Proposed Solution Design system to interface the sensors to the computer Analog Sampling of any number of sensors FPGA logic to control the system Semi-Real time wireless transmission to computer

4. System Block Diagram Sensors Analog MultiplexorA/DFPGA RF TransmitterRF ReceiverComputer Interface Clock Clock 1 Clock 2

5. Sensors Reflective Photosensors – Panasonic CNB2001 – 10 series to properly model golf ball – 5.1V – Up to ½” detection – Already provided by Mechanical Group Positional Sensors – 3 MEM’s Accelerometers to model x-y-z movement – 3 MEM’s Gyroscope to model x-y-z rotation – To be provided by Mechanical Group We will design for 16 sensors

6. Multiplexor & A/D Maxim DG406DJ – 16 to 1 Mux/DeMux – CMOS Analog – 1.25mW Low Power Consumption – At 5.1V we can detect analog signals up to 5V – Tried and True Maxim MAX172ACNG – 12-Bit A/D – 215mW still Low Power – 90ns data access time & 75ns bus release time are faster than our specs – Analog input voltage range 0-5V

7. FPGA Xilinx XC4010E – Used for development Choose a FPGA chip for PCB based on power and logic requirements – Tried and True Xilinx Development Software – Familiar (Digital Logic 3100)

8. FPGA Subsystems Clock Driving – 4*320 kHz = 1.280 MHz input (external clock) – Pulse outputs Pulse 1 to Multiplexor Pulse 2 to A/D Converter Pulse 3 to FPGA (internal driver) Counters from Pulse 3 – Output pin high every 16 th Pulse 3 for high-rate buffer write – Output pin high every 200 th Pulse 3 for write to transmission buffer at 100 Hz (hold high for all 16 sensors which is 16 Pulse 3’s)

9. FPGA Subsystems (cont.) Counters from inputs – When calibration button pressed, set calibration bit high for 1 second (100 pulses of transmission buffer enable) – Output high for 2 seconds after impact (enables high-rate buffer output) – Output high 1ms after impact (disables high-rate buffer input) High-rate buffer – When Pulse 3 high and not disabled write 12 bit input to buffer – When enabled write output at transmission buffer input rate

10. FPGA Subsystems (cont..) Transmission buffer – Inputs at 19.2 kbps out at 20 kbps but hold for first 8 clock pulses of each packet cycle (syncs RF and data input) Impact logic – Output one pin high when impact detected – Only check for impact on 16 th Pulse 3 (high-rate data is on input pins)

11. Computer Interface Serial Interface at minimum to verify accurate data delivery to PC (for Expo purposes) Decoder Software of Serial stream is necessary Hardware handshaking at RF output may be utilized to arrange data

12. Wireless System Abacom Tech Transmitter TXM-433-F – Freq: 433.92MHz – WxLxH 10.7x30x6mm – Radiated Power: 0.25mW – 20Kbps max – 300ft Abacom Tech Receiver SILRX-433-F – Matches with the TXM- 433-F – Internal memory recovery for easy decoding – WxLxH 20x48x6mm

13. Data-Packets 200-bit Data Packet – 6-bit Header Sequence (placeholders for now) – 1-bit calibration 1 = Calibration Set 0 = Normal Set – 1-bit high-rate (for use with force and impact duration calculations) 1 = Sensor Data bits are transmitting the high-rate data from buffer 0 = Real Time Data transmitting – 16 12-bit Sensor Data – 6+1+1+16(12)=200bit

14. Power All components powered at 5 Volts or less (3.6V possible implementation) Bench Power for development and testing Disposable Battery power for prototype; as small as possible

15. User Interface Switches and Buttons – Power On/Off button – Reset button – Calibration button LED’s – 1 Green LED ON when power switch is ON OFF when power switch of OFF – 1 Red LED ON when power switch is turned on OFF when reset is completed – 1 Yellow LED ON when calibration data is being taken

16. Division of Labor FPGA State Design (Kurt, Andy, Justin, Brian) RF transmission (Justin, Andy) Sensor/MUX/A-D Integration (Brian, Andy) Power (Kurt, Brian) Full Integration (Kurt, Andy) PCB Packaging (Justin) ME/PING Liaison (Brian) Documentation (Kurt, Brian, Andy, Justin)

17. Contingencies Data Display and Presentation alternatives – Serial, Parallel, USB, Graphing, GUI Meeting Size and Weight limitations PCB Packaging by Expo may be unrealistic – PING may have to wait a few weeks

18. Schedule

19. Deliverables Milestone 1 – Xilinx Computer Simulation of FPGA complete Milestone 2 – Capture System Integration Internal Expo – Capture/Transmit System Integration – Documentation

20. Updated Costs Development Costs (per unit): ~$400.00 – Sensors: ~$30.00 – Multiplexor: ~$2.00 – A/D: ~$28.00 – FPGA: ~$190.00 – Wireless System: ~$80.00 – Computer Interface: ~$30.00 Retail Costs – Parts: $400.00 – Manufacturing and Marketing: $800.00 – Suggested Retail Price Per Unit: $1.2k

21. Questions? Comments?