1. The Wait-er Hater WaitLoss Program utilizing WaitLess Technology: Presentation #3 Team M2: Jared Dubin Terry Garove Alex Runas Manager: Panchalam Ramanujan Overall Project Objective: Table/bar service interface controller chip 9/24/2007 Mis-Behavioral Verilog

2. Project Status Design proposal – complete Architecture - complete Name – … Size estimates/basic floorplan - complete RTL / Behavioral - complete Structural – incomplete Schematic Capture – incomplete Component layout and floorplan – incomplete Functional block layout and floorplan – incomplete Functional block LVS - incomplete

3. Updated Block Diagram

4. Updated FSM Flow

5. Updated Floorplan: Yet Another Version

6. Design Decisions: Pin-pricked - 1…2…3… 99??? - We’re running out of pins - In adding additional functionality to the FSM, the extra control signals have put us *dangerously* close to the maximum number of allotted I/O pins - Possible solutions: - (1) Limit number of item modification bits - Reduce total item-code to 20 bits total, saves 12 pins - (2) Encode item modification differently, no one-hot - Assume decoder exists off-chip… lame?

7. A Behavioral Model Behavioral Modules Behavioral Test

8. Issues/Concerns: Driving Home the Data - Wide, but relatively short bus - Accidental writes put us in the wrong - Weird “problem” to have, but there won’t be enough capacitance to distribute E(glitch) to prevent accidental writes - “Aggressive” wiring - Crosstalk issues possible with planned routing - “Now leaving the tri-state area” - How accurately can we plan for bus RC extractions when SRAM bus performance will determine chip characteristics to such a large degree