1. © ICU 전파교육연구센터 2003 1 성균관대학교정보통신공학부조준동 Software Defined Radio RF (Radio Frequency)

2. © ICU 전파교육연구센터 2003 2 Multiple Access Rf for SDR Micro Cell Macro Cell Smart Antenna Multi-mode Terminal by Software Radio MIMO Channel/ S-T Processing Diversity ITS

3. © ICU 전파교육연구센터 2003 3 Communications in RF

4. © ICU 전파교육연구센터 2003 4 다중모드 광대역 소형화 SDR RF 기술 Homodyne 설계 기술 (zero-IF 기술 )Homodyne 설계 기술 (zero-IF 기술 ) GSM2Plus + CDMA + 3GPP + 3GPP2 을 모두 수용하는 RF 회로GSM2Plus + CDMA + 3GPP + 3GPP2 을 모두 수용하는 RF 회로 ADC: 10W – 5Gsample/w 18-bit ADC: 10W – 5Gsample/w 18-bit 광대역 고주파 단일 부품의 구현이 불가능한 부품 ( 예 : Amp) 들에 대한 multi- band 부품 특성 구현을 위한 고주파 회로 기술 광대역 고주파 단일 부품의 구현이 불가능한 부품 ( 예 : Amp) 들에 대한 multi- band 부품 특성 구현을 위한 고주파 회로 기술 전자파 간섭 및 잡음 제거 기술, 전자파 간섭 및 잡음 제거 기술, SDR 용 Smart 안테나SDR 용 Smart 안테나

5. © ICU 전파교육연구센터 2003 5 Smart antenna Combination of Array Processing and Space- Time Coding ⇒ Capacity Maximization with Diversity and Coding Gain without Bandwidth Expansion ⇒ Capacity Maximization with Diversity and Coding Gain without Bandwidth Expansion Desired User Interferer Coherent Multipath Scatterers Direct Path Null

6. © ICU 전파교육연구센터 2003 6 High-Speed Packet Transmission by High-Speed Packet Transmission by M-ary modulation and Multiple Antenna M-ary modulation and Multiple Antenna Highly Spectral & Spatial Efficient Highly Spectral & Spatial Efficient Transmission Transmission Optimum Transmit Symbol Set for Optimum Transmit Symbol Set for Maximizing Channel Capacity Maximizing Channel Capacity Efficient Combining of Spatial & Efficient Combining of Spatial & Temporal Diversity Temporal Diversity - Layered Space-Time Processing - Layered Space-Time Processing - Combination of Channel Coding and - Combination of Channel Coding and Diversity Diversity Space-Time Processing

7. © ICU 전파교육연구센터 2003 7 Array Antenna types, SDR forum Type IType I –employ multiple antenna elements –employ RF combiners such as Butler Matrix. –a set of multiple feeds to the RF element. Type IIType II –includes the features of type I with one or more RFs – RF combiner with beamformer Type IIIType III –the most sophisticated antenna system. –the features of types I and II along with baseband combiner with beamformer along with baseband combiner with beamformer

8. © ICU 전파교육연구센터 2003 8 SDR 기반의 기지국 스마트 안테나 A. Xavier, J. Razavilar and K. J. R. Liu

9. © ICU 전파교육연구센터 2003 9 Conceptual RF/IF Types DAC & ADC 1st IFRFRF Channel Selector Baseband Processing DAC & ADC Channel Selector Baseband Processing DAC & ADC RF Channel Selector Baseband Processing DAC & ADC 1st IF RFRF 2nd IF Channel Selector Baseband Processing RF 1st IFRF 1st IF 2nd IF T R T R T R R T RF/IF Type I RF/IF Type II RF/IF Type III RF/IF Type IV 3 SDR Forum

10. © ICU 전파교육연구센터 2003 10 RF/IF Type I 4 SDR Forum Two stages to frequency translate toTwo stages to frequency translate to the IF frequency input to the the IF frequency input to the demodulator/ADC demodulator/ADC Filters used to optimize the bandwidthFilters used to optimize the bandwidth and eliminate noise and eliminate noise Requires accurate and stable LocalRequires accurate and stable Local Oscillators, and the LNA Oscillators, and the LNA

11. © ICU 전파교육연구센터 2003 11 RF/IF Type II 4 SDR Forum One stages to frequency translate toOne stages to frequency translate to the IF frequency input to the the IF frequency input to the demodulator/ADC demodulator/ADC Filters used to optimize the bandwidthFilters used to optimize the bandwidth and eliminate noise and eliminate noise Requires accurate and stable LocalRequires accurate and stable Local Oscillators, and the LNA Oscillators, and the LNA

12. © ICU 전파교육연구센터 2003 12 RF/IF Type III 4 RF signal after filtering and amplification isRF signal after filtering and amplification is applied directly to the demodulator/ADC applied directly to the demodulator/ADC LNA on the receive side tends toLNA on the receive side tends to limit linearity limit linearity RF/IF Type IV RF/IF Type IV RF signal is converted directly to digitalRF signal is converted directly to digital format using an ultra high speed ADC/demodulator to produce the baseband bit stream Digital Channel SelectionDigital Channel Selection

13. © ICU 전파교육연구센터 2003 13 Digital vs. Analog Conversion Analog LO Digital LO BP ADC Digital LPF Analog BPF & Amp Analog Mixer Analog LPF Analog Digital LP ADC Digital Mixer RF/IF Type IV

14. © ICU 전파교육연구센터 2003 14 Mixed Conversion Analog and Digital Analog and Digital RF 1st IF analog RF in Low Pass Filter Rec. IF Out Analog High Pass Filter Sin{F c +F m +VCOR1} +Sin{F c +F m -VCOR1} Sin{F c + F m -VCOR1} VCOR1 RF out VCOT2 Tran IF Analog = Sin{F c +F m } Sin{IF t +F m +VDOT2} + Sin{VCOT2 - IF t +F m } = Sin{VCOT1+If in +F m } = Analog IF Stage 2nd IF Digital ADC Clk1 Digital Local OSC Freq. Tuning Receiver Sin Digital Complex Mixer Cos Digital Low Pass Filter with Decimation Polyphase Interpol. Filter & Re-sampler Decimation Control & Filter Filter Coefficients I Q Re-Sampling Digital OSC DAC High Pass Digital Filter Digital Local OSC Sin Freq. Tuning Transmit Filter Coefficients 11 SDR Forum

15. © ICU 전파교육연구센터 2003 15 Conventional Heterodyne Multi-Mode Radio Receiver GSM 1800 BT / 802.11 UMTS GSM 1800 BT / 802.11 LO1 UMTS Legend BT / 802.11 2G Cellular 3G Cellular Low-Pass0.200- MHz BW LO2 10-MHz Low-Pass FDD Mode 1 FDD Mode 2 LO4 LO5 LO6 5.0-MHz BW 1.25-MHz Ch l 1.25-MHz Ch 2 1.25-MHz Ch 3 LO3 10-MHz Low-Pass 1.0-MHz BW Low-Pass LO7

16. © ICU 전파교육연구센터 2003 16 Homodyne Multi-Mode Radio Receiver Programmable Channel Filter I Q A/D Converter GSM 802.11 UMTS GSM 802.11 UMTS LO

17. © ICU 전파교육연구센터 2003 17 A Digital Receiver for Wideband Signal ChannelSeparationSymbolDetectionErrorDecoderSourceDecoder Channel decoder user Distortion caused by the channel Additive interfering signals Additive interfering signals random noise signals random noise signals delayed versions of the same signal delayed versions of the same signal Where Sn= signal of interest, I = interfering signals nn= random noise component

18. © ICU 전파교육연구센터 2003 18 Typical Processing For Narrow Band Channel Selection FilterDecimator Complex sinusoidal Frequency translation Bandwidth reduction Sampling rate reduction

19. © ICU 전파교육연구센터 2003 19 Wideband Channel selection Cascade of multiple FIR filterCascade of multiple FIR filter – bandwidth reduction in several stages – a lower number operations per output samples Filter bankFilter bank –multiple narrowband channels extracted from the same wideband simultaneously. –Computing the multiple output at a lower cost than multiple single channel. Cascade integrator comb filterCascade integrator comb filter –cascaded stages of accumulator w/ a pass band filter using no multiplication operations

20. © ICU 전파교육연구센터 2003 20 Digital Baseband Receiver RF input = 2GHz) LNA RF filter chip boundary I (50MS/s) Q (50MS/s) A/D AnalogDigital sin(w o t) cos(w o t) Crystal Zero IF Zero IF QPSK Demodulation

21. © ICU 전파교육연구센터 2003 21 BWRC’s Receiver Prototype Area = 4 mm 2 Noise Figure = 8.5 dB 90 kHz < f < 18 MHz PLL Phase Noise:  85 dBc/Hz @ 2.5 MHz LO-to-RF Leakage =  81 dBm  Dynamic Range = 42 dB @ 200 MHz Power Dissipation = 106 mW LNA mixer PLL baseband filters I  Q  0.25-  m, 6-metal CMOS process Jan Rabaey

22. © ICU 전파교육연구센터 2003 22 Six-port Digital receiver (Schiel et.al, E. Polytechnique de Montreal, CA) Application Specific Six-port Matching Circuits & Shottkey Diodes Wideband Video Amplifiers QPSK Decoder With TTL I&Q outputs Schottky Diodes HSMS-2850 OPA-2658U OP-Amp G=20dB High-speed Compensaters TL3016

23. © ICU 전파교육연구센터 2003 23 Digital vs. Analog Conversion 15Msps ~ 60Msps 10bits ~ 14bits

24. © ICU 전파교육연구센터 2003 24 ADC directly behind the antenna of a 900 MHz GSM receiver would require N=18 for 100 dB SNR and a sample rate of 2 for 100 dB SNR and a sample rate of 2 GHz, leading to a 36 Gbit/s ADC and a power consumption is 10–100 W, which is GHz, leading to a 36 Gbit/s ADC and a power consumption is 10–100 W, which is 1000 times higher than existing low-IF 1000 times higher than existing low-IF ADCs that consume around 10-15 mW. ADCs that consume around 10-15 mW.

25. © ICU 전파교육연구센터 2003 25 Wideband Spread Spectrum Radio Direct conversion architecture: –Simplifies analog RF design –Well-suited to single-chip CMOS integration –No IF stage: eliminates image reject problem –Primary challenge: DC offsets Wideband CDMA zero IF receiver, Phillips C. Teuscher, N. Zhang, D. Yee, Prof. R.W. Brodersen x x 0 90 o LNAAGC f osc In Phase (I) Quadrature (Q) RF Filter A/D o

26. © ICU 전파교육연구센터 2003 26 Receiver Block Diagram RF to Baseband High Speed A/D RF Filter Analog IC Carrier and Timing Sync. Channel Estimation Adaptive Multiuser Detection Data Out 3.3 Mbps Digital IC Ultimate objective: fully integrated, single chip radio

27. © ICU 전파교육연구센터 2003 27 Analog Baseband Section 1. Suppress out-of-band interference: RF filters do not provide adequate rejectionRF filters do not provide adequate rejection Interference profile influences the designInterference profile influences the design 2. High speed analog to digital conversion: Large dynamic range requirementsLarge dynamic range requirements Severe power constraintsSevere power constraints 32 MHz b a 1.96 GHz In band interference Near band interference Far band interference Frequency Interference Level

28. © ICU 전파교육연구센터 2003 28 Analog Baseband Fundamental tradeoff between speed of ADC and complexity of anti-alias filterFundamental tradeoff between speed of ADC and complexity of anti-alias filter Combined performance determines the maximum out-of-band interference levelsCombined performance determines the maximum out-of-band interference levels Current focus: energy-efficient implementationsCurrent focus: energy-efficient implementations

29. © ICU 전파교육연구센터 2003 29 A/D Converter: Power vs. Performance Digital radios will require high speed, low power, high resolution A/D converters Commercially Available A/D Converters (1998)

30. © ICU 전파교육연구센터 2003 30 Digital Baseband: Design Issues 50 MHz 25 MHz 2X Oversampled Receive Signal Data Out Adaptive Channel Estimation Adaptive Multiuser Detection 3.3 Mbps Carrier and Timing Synchronization Algorithm: Pilot channel-assisted adaptive MUDAlgorithm: Pilot channel-assisted adaptive MUD Modes of operation: blind, decision-directed, training sequence basedModes of operation: blind, decision-directed, training sequence based Key design metrics: power, area, performance, costKey design metrics: power, area, performance, cost Use advanced semiconductor technology

31. © ICU 전파교육연구센터 2003 31 Architectural Design Choices Flexibility Power Consumption General Purpose Microprocessor mP Prog Mem Software Programmable DSP MAC Unit Addr Gen mP Prog Mem Hardware Reconfigurable Processor Satellite Processor Satellite Processor Satellite Processor Prog Mem- mP Direct Mapped Hardware ASIC

32. © ICU 전파교육연구센터 2003 32 Example: Adaptive Pilot Correlator 50 MHz 25 MHz 2X Oversampled Receive Signal Data Out Carrier and Timing Synchronization Adaptive Data Correlator 3.3 Mbps Adaptive Pilot Correlator Adaptive Pilot Correlator... c1c1 cLcL Each APC provides one multipath channel estimateEach APC provides one multipath channel estimate Computational complexity of each APC:Computational complexity of each APC: –300M multiplications per second –357M additions/subtractions per second

33. © ICU 전파교육연구센터 2003 33 Technology Comparison *TMS320LC54X TI Low-Power DSP* Direct Mapped IC Process Technology Linewidth 0.35 m m0.25 m m Threshold VoltageDual V T : 0.4V, 0.2V 0.5V Supply Voltage 1V Clock Rate65 MHz25 MHz Wordlength1612 Flexibility Software Prog. Hard Wired

34. © ICU 전파교육연구센터 2003 34 Comparison: Power and Die Area DSP implementation is very inefficient: 100-150 times more power 100-150 times more power 450-700 times more area 450-700 times more area DSPDirect Mapped Digital Baseband Receiver Power1500 mW15 mW Area3600 mm 2 8 mm 2

35. © ICU 전파교육연구센터 2003 35 1st Approach: DSP Implementation 35 parallel processors required for real-time operation35 parallel processors required for real-time operation Each processor requires 1.6M transistors on a 31mm 2 dieEach processor requires 1.6M transistors on a 31mm 2 die Total power consumption: 460 mWTotal power consumption: 460 mW Breakdown of execution time and power consumption:Breakdown of execution time and power consumption: Execution TimePower Consumption Arithmetic Instructions35%36% Load/Store Instructions29%35% Control Instructions22%17% Memory Instructions14%12% Total100%

36. © ICU 전파교육연구센터 2003 36 2nd Approach: Direct Mapped Architecture Custom datapath designCustom datapath design Optimized parallel hardware with minimum controlOptimized parallel hardware with minimum control Reduced memory accessesReduced memory accesses Power and area dominated by MACs, multipliers, and register filesPower and area dominated by MACs, multipliers, and register files

37. © ICU 전파교육연구센터 2003 37 Programmable vs. Dedicated Power consumption: –Memory access overhead –Control overhead –Wordlength overhead –Assembly code optimization Area: –MAC units operate only 10% of the time –On-chip memory consumes 75% of the area –Arithmetic units less optimized Flexibility: –Level of programmability required (software, hardware, other), Time to market issues

38. © ICU 전파교육연구센터 2003 38 Approach to Low Power Design Minimize supply voltage: –Architecture driven voltage scaling Minimize physical capacitance: –Minimum feature sizes –Interconnect Minimize switching activity: –Algorithmic, architectural, numeric, and circuit-level optimizations –Power down Power = C L V DD 2 f CLK Optimize design across all levels

39. © ICU 전파교육연구센터 2003 39 Supply Voltage Optimization Delay (ns) Supply Voltage (V) 0.25  m process 0.6  m process 16 bit Ripple Adder Use the lowest possible supply voltage that satisfies throughput constraints: 1VUse the lowest possible supply voltage that satisfies throughput constraints: 1V Advanced process simultaneously improves performance and reduces power consumptionAdvanced process simultaneously improves performance and reduces power consumption

40. © ICU 전파교육연구센터 2003 40 Finite Wordlength Optimization Output SIR (dB) Symbol Times 8 bit 10 bit 12 bit 16 bit Fixed point arithmetic reduces power and area requirementsFixed point arithmetic reduces power and area requirements 12 bit wordlength suffices for this application12 bit wordlength suffices for this application

41. © ICU 전파교육연구센터 2003 41 Power Amplifier PSK or QAM requires linear transmitter amplifiersPSK or QAM requires linear transmitter amplifiers OFDM needs distortion reduction to increase power conversion efficiencyOFDM needs distortion reduction to increase power conversion efficiency Adaptive signal processing is effectiveAdaptive signal processing is effective Monolithic SiGe HBT Power Amplifier for Dual-Mode (CDMA/AMPS) Cellular HandsetMonolithic SiGe HBT Power Amplifier for Dual-Mode (CDMA/AMPS) Cellular Handset

42. © ICU 전파교육연구센터 2003 42 IBM2018 – 800 MHz CDMA/AMP Power Amplifier IS-95 CDMA/AMPS 824-849 MHzIS-95 CDMA/AMPS 824-849 MHz 2-stage LGA Module/ 50 Ohm I/O2-stage LGA Module/ 50 Ohm I/O Digital Power Up/Down ControlDigital Power Up/Down Control Analog Variable Efficiency ControlAnalog Variable Efficiency Control

43. © ICU 전파교육연구센터 2003 43 Conclusion Zero IF ArchitectureZero IF Architecture Required significant improvements in ADC performanceRequired significant improvements in ADC performance power:10W – 5Gsample/w 18-bit power:10W – 5Gsample/w 18-bit The transmit part : Power AmplifierThe transmit part : Power Amplifier The receive part : FilterThe receive part : Filter Analog Digital Using Fast DSP