# ECE 331 – Digital System Design Flip-Flops and Registers (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals.

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ECE 331 – Digital System Design Flip-Flops and Registers (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Fall 2010ECE 331 - Digital System Design2 Material to be covered … Chapter 11: Sections 6 – 8 Chapter 12: Sections 1 – 2

Fall 2010ECE 331 - Digital System Design3 Flip-Flops (continued)

Fall 2010ECE 331 - Digital System Design4 An S-R flip-flop is similar to an S-R latch in that S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0. The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge. SR Flip-Flop

Fall 2010ECE 331 - Digital System Design5 Operation summary: S = R = 0no state change S = 1, R = 0set Q to 1 (after active Ck edge) S = 0, R = 1reset Q to 0 (after active Ck edge) S = R = 1not allowed SR Flip-Flop

Fall 2010ECE 331 - Digital System Design6 SR Flip-Flop (master-slave)

Fall 2010ECE 331 - Digital System Design7 SR Flip-Flop: Timing Diagram

Fall 2010ECE 331 - Digital System Design8 The J-K flip-flop is an extended version of the S-R flip-flop. The J-K flip-flop has three inputs – J, K, and the clock (CK). The J input corresponds to S, and K corresponds to R. Unlike the S-R flip-flop, a 1 input may be applied simultaneously to J and K, in which case the flip-flop changes state (i.e. toggles) after the active clock edge. JK Flip-Flop

Fall 2010ECE 331 - Digital System Design9 JK Flip-Flop } Q + = Q } Q + = 0 } Q + = 1 } Q + = Q' set reset store toggle

Fall 2010ECE 331 - Digital System Design10 JK Flip-Flop (master-slave)

Fall 2010ECE 331 - Digital System Design11 JK Flip-Flop: Timing Diagram

Fall 2010ECE 331 - Digital System Design12 The T flip-flop, also called the toggle flip-flop, is frequently used in building counters. It has a T input and a clock input. When T = 1 the flip-flop changes state after the active edge of the clock. When T = 0, no state change occurs. T Flip-Flop

Fall 2010ECE 331 - Digital System Design13 Q + = T'Q + TQ' = Q  T T Flip-Flop

Fall 2010ECE 331 - Digital System Design14 T Flip-Flop: Timing Diagram

Fall 2010ECE 331 - Digital System Design15 Building a T Flip-Flop

Fall 2010ECE 331 - Digital System Design16 Asynchronous Control Signals

Fall 2010ECE 331 - Digital System Design17 Asynchronous Control Signals: Timing Diagram

Fall 2010ECE 331 - Digital System Design18 D FF with Clock Enable

Fall 2010ECE 331 - Digital System Design19 Registers

Fall 2010ECE 331 - Digital System Design20 Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. A better approach is to use registers with clock enables if they are available. Registers

Fall 2010ECE 331 - Digital System Design21 Register: 4 bits

Fall 2010ECE 331 - Digital System Design22 Transferring data between registers is a common operation in digital systems. Data can be transferred from the output of one of two registers into a third register using tri-state buffers. Data Transfer between Registers

Fall 2010ECE 331 - Digital System Design23 Data Transfer between Registers

Fall 2010ECE 331 - Digital System Design24 Register with Tri-state Output

Fall 2010ECE 331 - Digital System Design25 Data Transfer using Tri-state Bus

Fall 2010ECE 331 - Digital System Design26 A shift register is a register in which binary data can be stored and shifted either left or right. The data is shifted according to the applied shift signal; often there is a left shift signal and a right shift signal. A shift register must be constructed using flip-flops (i.e. edge- triggered devices); it cannot be constructed using latches or gated-latches (i.e. level-sensitive devices). Shift Register

Fall 2010ECE 331 - Digital System Design27 Shift Register: 4 bits

Fall 2010ECE 331 - Digital System Design28 Shift Register (4 bits): Timing Diagram

Fall 2010ECE 331 - Digital System Design29 8-bit SI SO Shift Register

Fall 2010ECE 331 - Digital System Design30 8-bit Shift Register: Timing Diagram

Fall 2010ECE 331 - Digital System Design31 4-bit PI PO Shift Register

Fall 2010ECE 331 - Digital System Design32 4-bit PI PO Shift Register: Operation

Fall 2010ECE 331 - Digital System Design33 4-bit PI PO Shift Register: Timing Diagram

Fall 2010ECE 331 - Digital System Design34 Parallel Adder with Accumulator

Fall 2010ECE 331 - Digital System Design35 In computer circuits, it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it, leaving the result stored in the register. Parallel Adder with Accumulator

Fall 2010ECE 331 - Digital System Design36 n-bit Parallel Adder with Accumulator

Fall 2010ECE 331 - Digital System Design37 Before addition in the previous circuit can take place, the accumulator must be loaded with X. This can be accomplished in several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops, and then put the X data on the Y inputs to the adder and add the accumulator in the normal way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator. Loading the Accumulator

Fall 2010ECE 331 - Digital System Design38 Adder Cell with Multiplexer

Fall 2010ECE 331 - Digital System Design39 Questions?

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