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1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-1 Chapter Five The Processor: Datapath and Control (Parte C: microprogramação)

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Presentation on theme: "1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-1 Chapter Five The Processor: Datapath and Control (Parte C: microprogramação)"— Presentation transcript:

1 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-1 Chapter Five The Processor: Datapath and Control (Parte C: microprogramação)

2 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-2 Complex instructions: the "next state" is often current state + 1 Another Implementation Style

3 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-3 Visão geral Memória de MicroControle PC INCR CC (tabelas) IR OP End Dados seq Unidade de controle programado IR

4 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-4 controle

5 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-5 Microprogramming What are the microinstructions ?

6 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-6 Diagrama de transição de estados PCWrite PCSource = 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUSrcA =1 ALUSrcB = 00 ALUOp= 10 RegDst = 1 RegWrite MemtoReg = 0 MemWrite IorD = 1 MemRead IorD = 1 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 RegDst=0 RegWrite MemtoReg=1 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 Instruction fetch Instruction decode/ register fetch Jump completion Branch completionExecution Memory address computation Memory access Memory access R-type completion Write-back step ( O p = ' L W ' ) o r ( O p = ' S W ' ) ( O p = R - t y p e ) ( O p = ' B E Q ' ) ( O p = ' J ' ) ( O p = ' S W ' ) ( O p = ' L W ' ) Start

7 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-7 Um microprograma horizontal

8 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-8 A specification methodology –appropriate if hundreds of opcodes, modes, cycles, etc. –signals specified symbolically using microinstructions Will two implementations of the same architecture have the same microcode? What would a microassembler do? Microprogramming

9 Microinstruction format

10 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-10 No encoding: –1 bit for each datapath operation –faster, requires more memory (logic) –used for Vax 780 an astonishing 400K of memory! Lots of encoding: –send the microinstructions through logic to get control signals –uses less memory, slower Historical context of CISC: –Too much logic to put on a single chip with everything else –Use a ROM (or even RAM) to hold the microcode –Its easy to add new instructions Maximally vs. Minimally Encoded

11 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-11 Microcode: Trade-offs Distinction between specification and implementation is sometimes blurred Specification Advantages: –Easy to design and write –Design architecture and microcode in parallel Implementation (off-chip ROM) Advantages –Easy to change since values are in memory –Can emulate other architectures –Can make use of internal registers Implementation Disadvantages, SLOWER now that: –Control is implemented on same chip as processor –ROM is no longer faster than RAM –No need to go back and make changes

12 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5B-12 The Big Picture Initial representation Finite state diagram Microprogram Sequencing control Explicit next state function Microprogram counter + dispatch ROMS Logic representation Logic equations Truth tables Implementation technique Programmable logic array Read only memory Ler Historical perspective and further reading RISC x CISC Controle hardwired microprogramado (firmware)


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