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Some examples Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it Lecture 7.3

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2 7.3 Goal This lecture guides the students through the solution of some simple examples of manual synthesis of sequential networks.

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3 7.3 Prerequisites Lectures 7.1 and 7.2

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4 7.3 Homework Students are recommended to try to solve the exercise by themselves, before looking at the proposed solutions.

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5 7.3 Further readings No particular suggestion

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6 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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7 7.3 Example #7.3.1: rising edge detector A circuit is to be designed, having: An input X A clock signal CLK, which acts as a proper sampling signal of X, i.e., the frequency of CLK is such that it never happens that two transitions of X occur within a same CLK cycle An output U, asserted for a clock cycle whenever a rising edge on the input X is detected.

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8 7.3 CLK X Waveforms

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9 7.3 CLK X Z Waveforms

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10 7.3 STG reset H0,0

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11 7.3 STG reset 1 H0,0

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12 7.3 STG L,0 reset 1 0 H0,0

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13 7.3 STG L,0 reset 1 0 0 H0,0

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14 7.3 STG L,0 H1,1 reset 1 0 1 0 H0,0

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15 7.3 STG L,0 H1,1 reset 1 0 1 0 H0,0 0

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16 7.3 STG L,0 H1,1 reset 1 0 1 0 H0,0 0 1

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17 7.3 State encoding stateencoding H000 L11 H110

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STT L,0 H1,1 reset 1 0 1 0 H0,0 0 1 stateencoding H000 L11 H110

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STT L,0 H1,1 reset 1 0 1 0 H0,0 0 1 stateencoding H000 L11 H110 01 H0 0011 00 0 01 - - 0 L 11 11 10 0 H1 1011 00 1 y[1:0] x Y[1:0] Z

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20 7.3 STT 01 H0 0011 00 0 01 - - 0 L 11 11 10 0 H1 1011 00 1 y[1:0] x Y[1:0] Z Y[1] = x’ + y[0] Y[0] = x’ Z = y[1]y[0]’

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21 7.3 D D x Z D[1] = x’ + y[0] D[0] = x’ Z = y[1]y[0]’ Solution D[0] y[1] y[0] D[1]

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22 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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23 7.3 Example #7.3.2: palindrome string detector On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.

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24 7.3 Example #7.3.2: palindrome string detector On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string. Examples: ANNA – 3993 – 0110

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25 7.3 - 0 1 reset

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26 7.3 - 0 1 0 1 0 1 0 1 reset

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27 7.3 - 0 1 01 11 00 10 0 1 0 1 0 1 0 1 0 1 1 0 0 1 reset

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28 7.3 - 0 1 01 11 00 10 011 111 000 100 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 reset

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29 7.3 - 0 1 01 11 00 10 011 111 000 100 0110 1111 0000 1001 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 01 1 0 1 0 0 1 U=0 U=1 reset

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30 7.3 - 0 1 01 11 00 10 011 111 000 100 0110 1111 0000 1001 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 01 1 0 1 0 0 1 U=0 U=1 reset

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31 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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32 7.3 Example #7.3.3: BCD big endian On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 4 bits: each group corresponding to a BCD digit, transmitted MSB first (big endian) A circuit to be connected to the serial line is to be designed. It has an output U which is asserted, for 1 clock cycle, in correspondence of the 4 th bit of each group, if the group itself is a correct BCD digit. BCD

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33 7.3 Solution When dealing with circuits that must consider groups of bits, it may be convenient to start from a set of states, one for each possible combination of the PO values. BCD

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34 7.3 Solution A,0E,1 reset 0 1 1 0 BCD

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35 7.3 Solution A,0E,1 B,0 reset 0 1 1 0 - BCD

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36 7.3 Solution A,0E,1 B,0 reset 0 1 1 0 C,0 - - BCD

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37 7.3 Solution A,0E,1 B,0 reset 0 1 1 0 C,0 D,0 - - - BCD

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38 7.3 Solution A,0E,1 B,0 F,0 reset 0 1 1 0 C,0 D,0 - - - BCD

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39 7.3 Solution A,0E,1 B,0 F,0 reset 0 1 1 0 C,0 D,0 - - H,0 1 - BCD

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40 7.3 Solution A,0E,1 B,0 F,0 reset 0 1 1 0 C,0 D,0 I,0 - - H,0 - 1 - - BCD

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41 7.3 Solution A,0E,1 B,0 F,0 reset 0 1 0 1 0 C,0G,0 0 D,0 I,0 - - H,0 - 1 1 - - BCD

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42 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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43 7.3 Example #7.3.4: BCD little endian Similar to the previous exercise, with the only difference that BCD digits are transmitted LSB first. BCD

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44 7.3 Valid Sequences 00000Y 00018Y 00104Y 001112N 01002Y 010110N 01106Y 011114N 10001Y 10019Y 10105Y 101113N 11003Y 110111N 11107Y 111115N BCD

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45 7.3 A,0E,1 B,0 reset C,0 F,0 D,0 G,0 1 0 1 0 E 0 1 EA BCD

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46 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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47 7.3 Example #7.3.5: parity checker On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit strings of 4 bits A circuit to be connected to the serial line is to be designed. It has an output Z which is asserted, for 1 clock cycle, in correspondence of the 4 th bit of each string, if the string itself contains an odd # of 1’s. P4P4P4P4

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48 7.3 Example X0100101011010000Z---1---0---1--0X0100101011010000Z---1---0---1--0 P4P4P4P4

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49 7.3 B,-C,- reset evenodd P4P4P4P4

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50 7.3 B,-C,- D,-E,- 00 11 reset evenodd P4P4P4P4

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51 7.3 B,-C,- D,-E,- F,-G,- 0 0 0 0 1 1 1 1 1 1 reset evenodd P4P4P4P4

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52 7.3 B,-C,- D,-E,- F,-G,- H,0I,1 0 0 0 0 0 0 1 1 1 1 1 1 reset evenodd P4P4P4P4

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53 7.3 reset B,-C,- D,-E,- F,-G,- H,0I,1 0 0 0 0 0 0 1 1 1 1 1 1 01 01 evenodd P4P4P4P4

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54 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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Example #7.3.6: Ford Thunderbird light controller A circuit is to be designed to control the back lights of the Ford Thunderbird of 1965. The car has,on its back, 6 lights, turned on with different strategies to signal different operations: Turn left Turn right Break Emergency

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56 7.3 t Turn to the right

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57 7.3 t Turn to the right

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58 7.3 t Turn to the right

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59 7.3 t Turn to the right

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60 7.3 t Turn to the right

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61 7.3 Turn to the left t

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62 7.3 t Brake Brake on Brake off

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63 7.3 t Emergency

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64 7.3 The circuit has: 4 inputs: LEFT & RIGHT asserted when turning left or right, respectively HAZ asserted to signal an emergency BRAKE asserted when the driver is braking 6 outputs, one for each light: Top level LCLBLARARBRC

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65 7.3 Input signals are assigned the following priority: BRAKE has the highest priority LEFT & RIGHT have the lowest priority HAZ has an intermediate priority Input priorities

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66 7.3 Solution To simplify the design, the BRAKE input can be implemented as follows, and thus not considered any longer in the sequel of the design: FSM BRAKE

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67 7.3 IDLE 000 LEFT, RIGHT, HAZ STG

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68 7.3 IDLE LCLBLARARBRC 000 LEFT, RIGHT, HAZ STG

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69 7.3 1 IDLELR3 LCLBLARARBRC LEFT, RIGHT, HAZ

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70 7.3 IDLELR3 LCLBLARARBRC LEFT, RIGHT, HAZ

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71 7.3 IDLE L1 LR3 LCLBLARARBRC 100 LEFT, RIGHT, HAZ

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72 7.3 IDLE L2 L1 LR3 LCLBLARARBRC 0 LEFT, RIGHT, HAZ

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73 7.3 L3 IDLE L2 L1 LR3 LCLBLARARBRC 0 LEFT, RIGHT, HAZ

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74 7.3 L3 IDLE L2 L1 LR3 LCLBLARARBRC LEFT, RIGHT, HAZ

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75 7.3 L3 IDLE L2 L1 R1 LR3 LCLBLARARBRC 010 LEFT, RIGHT, HAZ

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76 7.3 L3 IDLE L2 L1 R2 R1 LR3 LCLBLARARBRC 0 LEFT, RIGHT, HAZ

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77 7.3 L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC 0 LEFT, RIGHT, HAZ

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78 7.3 L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC LEFT, RIGHT, HAZ

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79 7.3 L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC 1 LEFT, RIGHT, HAZ

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80 7.3 L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC 1 LEFT, RIGHT, HAZ

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81 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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82 7.3 Example #7.3.7: code checker On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 5 bits. In each group, the first 3 bits are a data and the remaining 2 bits are a code associated to the data to detect transmission errors. In particular, for each group of bits, the code encodes the number of bits equal to ‘1’ in the data of the same group. Codes are transmitted Most Significant Bit (MSB) first. 3|2

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83 7.3 Example #7.3.7: code checker (cont’d) A circuit to be connected to the serial line is to be designed, such that its output OK is asserted for one clock cycle iff, at the completion of a group, no transmission error has been detected. 3|2

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84 7.3 STG ko,0 reset ok,1 0 0 1 1 3|2

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85 7.3 STG ko,0 reset ok,1 0 #0,0 0 #1,0 0 11 1 0 1 1 3|2

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86 7.3 STG ko,0 reset ok,1 0 #0,0 0 0 #1,0 0 1 1 1 0 1 0 1 #2,0 1 11 0 3|2

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87 7.3 STG ko,0 reset ok,1 0 #0,0 #1,0 0 0 #0,0 #1,0 0 1 1 1 0 1 0 1 #2,0 #3,0 1 11 1111 0 3|2 data

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88 7.3 STG ko,0 reset ok,1 0 #0,0 #1,0 0 0 #0,0 #1,0 0 1 1 1 0 1 0 1 #2,0 #3,0 1 11 A,0B,0C,0 1 0 111 000 okkookko 0 0 1 - 10 code 3|2

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89 7.3 Outline Example #7.3.1: rising edge detector Example #7.3.2: palindrome string detector Example #7.3.3: BCD big endian Example #7.3.4: BCD little endian Example #7.3.5: parity checker Example #7.3.6: Ford Thunderbird light controller Example #7.3.7: code checker Example #7.3.8: sequence checker

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90 7.3 Example #7.3.8: sequence checker On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit sequences of 1’s and sequences of 0’s. In particular, sequences may have any length, but all the sequences of 1’s must contain an odd # of 1’s, whereas all the sequences of 0’s must contain an even # of 0’s. A circuit to be connected to the serial line is to be designed, such that its output OK is asserted for one clock cycle whenever a transmission errors has been detected. odd even

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91 7.3 Solution hint Since the # of possible states is limited, list the whole set of states first fill up the transitions later erase the unreachable states (if any) odd even

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92 7.3 STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, 1 #0 even, 1 #1 even, 1 odd even

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93 7.3 STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, 1 0 0 0 0 0 0 1 1 1 1 1 1 #0 even, 1 #1 even, 1 odd even

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94 7.3 STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, 1 0 0 0 0 0 0 1 1 1 1 1 1 #0 even, 1 #1 even, 1 Unreachable states: they can be deleted odd even

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95 7.3 STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, 1 0 0 0 0 0 0 1 1 1 1 1 1 odd even

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