Presentation is loading. Please wait.

Presentation is loading. Please wait.

Low Power Memory. Quick Start Training Agenda What constitutes low power memory Variations & vendors of low power memory How to interface using CoolRunner-II.

Published byClaude Rodgers Modified over 9 years ago

Similar presentations

Presentation on theme: "Low Power Memory. Quick Start Training Agenda What constitutes low power memory Variations & vendors of low power memory How to interface using CoolRunner-II."— Presentation transcript:

1 Low Power Memory

2 Quick Start Training Agenda What constitutes low power memory Variations & vendors of low power memory How to interface using CoolRunner-II

3 Quick Start Training What is Low Power Memory Devices feature additional power saving options: – Advanced self refresh modes – Deep power down mode – Low voltage power supply (1.8V, 2.5V, 3.3V) – Low standby current – Automatic power down Advanced architecture and memory cell structure Advanced packaging options

4 Quick Start Training Advanced Architecture Improved cell structure – UtRAM: uni-transistor memory cell structure Prefetch architecture creates high speed devices

5 Quick Start Training TCSR Temperature Compensated Self Refresh Ambient temperature adjusts refresh rate – Capacitor loses charge quicker at high temperature – Decrease refresh rate at lower temperatures Minimized standby current during standby Selectable for: 15°C, 45°C, 70°C, 85°C Requires an external temperature sensor

6 Quick Start Training PASR Partial Array Self Refresh Specify which banks are enabled

7 Quick Start Training DPD Deep Power Down Maximum power reduction Memory data is not retained Acts as “soft switch-off”

8 Quick Start Training Available Devices Infineon MobileRAM (synchronous lower power DRAM) Cypress MoBL (mobile static RAM) Samsung – UtRAM – Low power SRAM – Mobile SDRAM Micron – Mobile SDRAM – Cellular RAM

9 Quick Start Training Mobile SDRAM Features Fully synchronous Internal pipeline architecture Programmable burst length (1, 2, 4, 8, page) TCSR PASR power saving self-refresh DPD Up to 70% power savings over standard SDRAM devices in self-refresh mode

10 Quick Start Training Mobile SDRAM Commands NOP (Deselect SDRAM device) ACTIVE (Opens row in specified bank for access) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) DEEP POWER DOWN (Maximum power savings, data is not retained) PRECHARGE (Deactivates open row in specified bank or all banks) AUTO REFRESH or SELF REFRESH (Retains data in SDRAM) LOAD MODE REGISTER (Defines operating mode of SDRAM)

11 Quick Start Training Timing Specifications For example, t RCD = 20 ns, with 125 MHz clock = 3 clock cycles Parameter t RCD = delay controller must wait between ACTIVE and a READ/WRITE command

12 Quick Start Training Read Command

13 Quick Start Training Write Command

14 Quick Start Training Deep Power Down Mode Upon exit DPD mode: NOP for 200 us Precharge all banks Issue 8 Auto Refresh commands Initialize Mode Register & Extended Mode Register

15 Quick Start Training Why CoolRunner-II Low standby current < 100 uA Easy system integration with memory devices Perfect target device for portable and handheld applications System Bus Mobile SDRAM

16 Quick Start Training CPLD Design

17 Quick Start Training State Machine Components CAS latency 2-bit counter Write burst 4-bit counter Read burst 4-bit counter (implements burst up to 8) Mode Register – CAS, burst length

18 Quick Start Training State Machine

19 Quick Start Training Conclusion Complete downloadable VHDL reference design: XAPP394 CoolRunner-II is the perfect target device for interfacing to low power memory devices – CoolRunner-II allows seamless system integration – CoolRunner-II is the ideal low power memory controller

Download ppt "Low Power Memory. Quick Start Training Agenda What constitutes low power memory Variations & vendors of low power memory How to interface using CoolRunner-II."

Similar presentations

Synchronous Static Random Access Memory (SSRAM). Internal Structure of a SSRAM AREG: Address Register CREG: Control Register INREG: Input Register OUTREG:

Synchronous Static Random Access Memory (SSRAM). Internal Structure of a SSRAM AREG: Address Register CREG: Control Register INREG: Input Register OUTREG:
Outline Memory characteristics SRAM Content-addressable memory details DRAM © Derek Chiou & Mattan Erez 1.

Outline Memory characteristics SRAM Content-addressable memory details DRAM © Derek Chiou & Mattan Erez 1.
Chapter 5 Internal Memory

Chapter 5 Internal Memory
Prith Banerjee ECE C03 Advanced Digital Design Spring 1998

Prith Banerjee ECE C03 Advanced Digital Design Spring 1998
Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.

Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.
COEN 180 DRAM. Dynamic Random Access Memory Dynamic: Periodically refresh information in a bit cell. Else it is lost. Small footprint: transistor + capacitor.

COEN 180 DRAM. Dynamic Random Access Memory Dynamic: Periodically refresh information in a bit cell. Else it is lost. Small footprint: transistor + capacitor.
Main Mem.. CSE 471 Autumn 011 Main Memory The last level in the cache – main memory hierarchy is the main memory made of DRAM chips DRAM parameters (memory.

Main Mem.. CSE 471 Autumn 011 Main Memory The last level in the cache – main memory hierarchy is the main memory made of DRAM chips DRAM parameters (memory.
DDR SDRAM Memory Interface. Quick Start Training Agenda Why DDR? DDR vs. SDR Understanding DDR SDRAM – Bus timing CoolRunner-II and DDR SDRAM demo board.

DDR SDRAM Memory Interface. Quick Start Training Agenda Why DDR? DDR vs. SDR Understanding DDR SDRAM – Bus timing CoolRunner-II and DDR SDRAM demo board.
CS.305 Computer Architecture Memory: Structures Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005, and from slides kindly made.

CS.305 Computer Architecture Memory: Structures Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005, and from slides kindly made.
Chapter 9 Memory Basics Henry Hexmoor1. 2 Memory Definitions  Memory ─ A collection of storage cells together with the necessary circuits to transfer.

Chapter 9 Memory Basics Henry Hexmoor1. 2 Memory Definitions  Memory ─ A collection of storage cells together with the necessary circuits to transfer.
DRAM. Any read or write cycle starts with the falling edge of the RAS signal. –As a result the address applied in the address lines will be latched.

DRAM. Any read or write cycle starts with the falling edge of the RAS signal. –As a result the address applied in the address lines will be latched.
Registers  Flip-flops are available in a variety of configurations. A simple one with two independent D flip-flops with clear and preset signals is illustrated.

Registers  Flip-flops are available in a variety of configurations. A simple one with two independent D flip-flops with clear and preset signals is illustrated.
Memory Key component of a computer system is its memory system to store programs and data. ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides12.ppt.

Memory Key component of a computer system is its memory system to store programs and data. ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides12.ppt.
1 COMP 206: Computer Architecture and Implementation Montek Singh Mon., Nov. 18, 2002 Topic: Main Memory (DRAM) Organization – contd.

1 COMP 206: Computer Architecture and Implementation Montek Singh Mon., Nov. 18, 2002 Topic: Main Memory (DRAM) Organization – contd.
Chapter 6 Memory and Programmable Logic Devices

Chapter 6 Memory and Programmable Logic Devices
Contemporary Logic Design Sequential Case Studies © R.H. Katz Transparency No. 21-1 Chapter #7: Sequential Logic Case Studies 7.6 Random Access Memories.

Contemporary Logic Design Sequential Case Studies © R.H. Katz Transparency No Chapter #7: Sequential Logic Case Studies 7.6 Random Access Memories.
NS9750 - Training Hardware. Memory Interface Support for SDRAM, asynchronous SRAM, ROM, asynchronous flash and Micron synchronous flash Support for 8,

NS Training Hardware. Memory Interface Support for SDRAM, asynchronous SRAM, ROM, asynchronous flash and Micron synchronous flash Support for 8,
CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent.

CSIT 301 (Blum)1 Memory. CSIT 301 (Blum)2 Types of DRAM Asynchronous –The processor timing and the memory timing (refreshing schedule) were independent.
Memory Technology “Non-so-random” Access Technology:

Memory Technology “Non-so-random” Access Technology:
Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Working with DRAM April 3, 2007.

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Working with DRAM April 3, 2007.

Similar presentations

Ads by Google