1. 7 th International Meeting on Front-End Electronics, Montauk NY – May 18 th - 21 st, 2009 Cyclic-ADC developments for Si calorimeter of ILC Laurent ROYER, on behalf of the MicRhAu designers collaboration

2. L.ROYER – FEE 09 @ Montauk – May 18-21, 20092 "Pole" MicRhAu: collaboration for µelectronics Laboratoire de Physique Corpusculaire de Clermont Ferrand Institut de Physique Nucléaire de Lyon  12 µelectronic designers  analog/mixed ASIC for physic experiments and applications (medical): MICro-electronic RHone AUvergne Collaboration for µelectronic designs: Charge preamplifier Shaper, filter ADC OTA, drivers T&H Comparators http://micrhau.in2p3.fr (still under construction)

3. L.ROYER – FEE 09 @ Montauk – May 18-21, 20093 Projects @ MicRhAu VFE for liquid argon TPC LHCb: preshower ALICE: dimuon trigger CMS: preshower & Ecal INNOTEP Readout chip for PET T2K ILC Readout chip for SiW Ecal Readout chip for DHcal Now TomorrowYesterday S-ATLAS S-CMS Under discussion … STAR Readout chip for ECG sensor LHC Taranis Etoile Si detector for satellite Beam Hodoscop of PM

4. L.ROYER – FEE 09 @ Montauk – May 18-21, 20094 ADC developments @ MicRhAu Resolution Speed Pipeline 10 bits – 4 MS/s 35 mW Cyclic 12 bits – 0.15 MS/s 3.5 mW 0.1 MS/s 1 MS/s 10 MS/s 100 MS/s 8 bits 10 bits 12 bits 6 bits Wilkinson 12 bits – 0.0125 MS/s 2.9 mW 0.01 MS/s Flash 6 bits * – 20 MS/s 1 mW Pipeline 8 bits – 100 MS/s 240 mW Flash 8 bits – 50 MS/s 60 mW * with missing code at high dynamic range

5. L.ROYER – FEE 09 @ Montauk – May 18-21, 20095 ILC: challenges for Si-W Calorimeter Sandwich structure of: thin wafers of silicon diodes (~200 µm) & tungsten layers High granularity : diode pad size of 5x5 mm 2 High segmentation : ~30 layers Large dynamic range (15 bits) 0.1 MIP -> ~3 000 MIPS Embedded Very Front End (VFE) electronics Minimal cooling available > 100.10 6 channels Ultra-low power : 25 µW per VFE channel Low POWER is the KEY issue (CdlT) « Tracker electronics with calorimetric performance »

6. L.ROYER – FEE 09 @ Montauk – May 18-21, 20096  Main requirements for the ADC: –Die area:  as small as possible… –Resolution:  12 bits with 2-gain shaping –Time of conversion: time budget of 500 µs to convert all data of all triggered channels –Ultra low power:  2.5 µW/ch (10% of the VFE power budget)  Memory depth of 5  0.5 µW per conversion  Power pulsing needed VFE electronics of Si-W Ecal Analog electronics busy 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) IDLE MODE 198ms (99%)

7. L.ROYER – FEE 09 @ Montauk – May 18-21, 20097 Single or multi-channel ADC ? Short analog sensitive wires from memory to ADC A digital Data Bus far from sensitive analog signals Only ADCs of triggered channels powered ON Conversions of channels done in parallel Integrity of analog signals saved Power saved  Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated With one-ADC-per-channel architecture: No "fast" ADC required Single-channel ADC scenario Multi-channel ADC scenario

8. L.ROYER – FEE 09 @ Montauk – May 18-21, 20098 One cycle = two phases of amplification and sampling At each cycle (one clock period), 2 bits are delivered  MSB then MSB-1, …..until LSB For an n-bit ADC, n/2 cycles are required The key block: gain-2 amplifier (switched capacitors amplifier)  The precision of the gain-2 amplification gives the precision of the ADC Conventional 2-stage Cyclic architecture MSB MSB-1 A1 A2 A1 A2  one cycle 

9. L.ROYER – FEE 09 @ Montauk – May 18-21, 20099 + 1 redundant bit at each cycle  Precision of the ADC becomes insensitive to the offset of the comparators up to ± 1/8 of the dynamic range (± 125mV for 2 V) Number of comparators is doubled 1,5 bit/stage Cyclic architecture

10. L.ROYER – FEE 09 @ Montauk – May 18-21, 200910 Enhanced architecture: "Flip-around amplifier " A single amplifier shared by the two stages As main of the power is consumed by amplifier  reduction of power up to 40% MSB MSB-1 AA  one cycle  A A

11. L.ROYER – FEE 09 @ Montauk – May 18-21, 200911 1 MHz clock "Start conversion " signal 1 2 3 4 5 6 11 10 12 8 9 7 Output signal of the amplifier Two phases of conversion with a single amplifier Enhanced architecture: "Flip-around amplifier "

12. L.ROYER – FEE 09 @ Montauk – May 18-21, 200912 The cyclic ADC designed Clock frequency: 1MHz Supply voltage : 3.5V Technology: 0.35 µm CMOS Austriamicrosystems (reliable and cheap !!) ADC designed with the validated building blocks (Amplifier & Comparator) of a 10-bit pipeline ADC (published in IEEE NSS in June 08) but optimized for the 12-bit precision requirement Power pulsing system implemented Digital process of the bits (1.5 bit/stage algorithm) performed by an external FPGA Fully differential ADC: analog signal, reference, clock… Die area of the core = 0.175mm2 "Fully-Differential Circuits have very good PSRR and cross-talk rejection" Michael K. … and also a good rejection of common mode noise induced by digital electronics

13. L.ROYER – FEE 09 @ Montauk – May 18-21, 200913 Comparator Measured performance  Sensitivity = input noise : < 280 µV (95% C.L.)  Offset: 20mV ± 9 mV (68 % C.L.)  far from the ± 125 mV tolerated by the 1.5bit/stage architecture Comparator  Fully differential latched architecture  Power consumption: 280µW

14. L.ROYER – FEE 09 @ Montauk – May 18-21, 200914 Amplifier  Fully differential and rail-to-rail  2 amplification stages  Resistive CMFB  Power consumption: 2870 µW Capacitive load (feedback + sampling): 3 x 0.8pF Requirement @ 12 bits/1MHz Performance Open Loop DC Gain  16k 19.6k Fc à -3dB 174 Hz2,5 kHz

15. L.ROYER – FEE 09 @ Montauk – May 18-21, 200915 Charge injection: Bottom plate sampling  S1 remains ON, S2 turns OFF Ground impedance smaller than1/j  (C F +C S )  charges mainly injected to the ground Residual charge is constant and cancelled by differential structure of the gain-2 amplifier  S1 turn OFF, S2 remains OFF Input (Vin) impedance smaller than 1/j  (C P +C J )  charges mainly injected back to the input Vin CFCF CsCs S1 S2 CFCF CsCs S1 CPCP CJCJ CJCJ Vin Hardware delay introduced between control signals of S1 & S2 gates

16. L.ROYER – FEE 09 @ Montauk – May 18-21, 200916 Measurement setup for ADC Test Bench:  Generic board for ADC tests  Analogue signal generator: DAC 16 bits (DAC8830)  PC/LabView Slow Control through USB interface  Data processing with Scilab package Chip under test USB link Static measurements :  Input ADC signal: ramp from 0 to 2V  > 4096 steps -- 50 measurements / step

17. L.ROYER – FEE 09 @ Montauk – May 18-21, 200917 Power pulsing measurement Master current sources switched OFF 1 µs for recovery time included after power ON Measurement of consumption with duty cycle power ON/OFF Integrated consumption with ILC timing : 0.12 µW per conversion

18. L.ROYER – FEE 09 @ Montauk – May 18-21, 200918 Measurements of the performance But Yield ≈ 60%  designed of a new "process-hard" gain-2 amplifier Differential Non-Linearity Noise Integral Non-Linearity DNL<+/-1 LSB No missing code Standard deviation = 0.84 LSB (420µV) INL<+/-1 LSB

19. L.ROYER – FEE 09 @ Montauk – May 18-21, 200919 New designs 4 new ADC with 4 new amplifiers designed and submitted to foundry in March Reduction of power supply voltage: 3.5V to 3.0V and optimization (reduction) of BW performance of the amplifier Improvement of the yield: reduction of biasing variation versus process fluctuation  single stage amplifier Layout of the chip submitted in March 09

20. L.ROYER – FEE 09 @ Montauk – May 18-21, 200920 New Amplifiers Folded cascode structure Current CMFB (reduced consumption) Folded cascode structure Voltage CMFB

21. L.ROYER – FEE 09 @ Montauk – May 18-21, 200921 New Amplifiers Folded cascode structure (different sizing of transistors) Voltage CMFB Boosted folded cascode structure Voltage CMFB

22. L.ROYER – FEE 09 @ Montauk – May 18-21, 200922 ArchitectureCMFBDC GainConsum.BW Folded cascodeVoltage23 k570 µW436 Hz Folded cascodeCurrent23 k450 µW318 Hz Boosted Folded cascodeVoltage22 k1470 µW1700 Hz Folded cascodeVoltage28 k1020 µW428 Hz New Amplifiers performance Previous amplifier consumption: 2870 µW Simulated INL of the 4 new ADC > 174Hz required

23. L.ROYER – FEE 09 @ Montauk – May 18-21, 200923 Summary  Measured performance in accordance with Si-W ECAL VFE requirements  Time conversion = 7µs  Consumption < 0.6µW per channel (analog memory depth of 5 and power pulsing included)  2.5% of the power budget of one VFE channel  Linearity: DNL < +/1 LSB & INL < +/-1 LSB  Standard deviation of Noise < 0.9 LSB  Improvement of consumption and of the yield expected with the design of the new amplifiers  chips have to be tested (received last week)  The acquired experience with this cyclic ADC can be exported to other project and/or to faster pipeline architecture

24. L.ROYER – FEE 09 @ Montauk – May 18-21, 200924 A cyclic "machine" ?? Thank you for your attention !!