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Unclassified High Speed Electronics Group Faculty of Electrical Engineering (1) RAFAEL, Armament Development Authority Ltd., Microelectronic Directorate.

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Presentation on theme: "Unclassified High Speed Electronics Group Faculty of Electrical Engineering (1) RAFAEL, Armament Development Authority Ltd., Microelectronic Directorate."— Presentation transcript:

1 Unclassified High Speed Electronics Group Faculty of Electrical Engineering (1) RAFAEL, Armament Development Authority Ltd., Microelectronic Directorate (2) Department of Electrical Engineering, Technion-Israel Institute of Technology T. Magrisso (1) D. Elad (1) N. Buadana (1) S. Kraus (2) D. Cohen Elias (2) A. Gavrilov (2) S. Cohen (2) D. Ritter (2)

2 Unclassified High Speed Electronics Group Faculty of Electrical Engineering InP Based VCOs Record frequencies Optoelectronic integration: Optoelectronic Oscillitor, Clock recovery, etc..

3 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Previous work on InP HBT circuits at Technion: 75 GHz TWA 43 GHz integrated TWA photoreceiver

4 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Varactors in InP HBT VCOs Previous InP HBT VCOs used base collector layers as varactor layers. Optimized HBT requires fully depleted collector at Vbc=0, for minimum VCO’s phase noise. As a results, small tuning range is obtained

5 Unclassified High Speed Electronics Group Faculty of Electrical Engineering InP Semi-insulating Substrate Ga InAs N+ Sub-Collector Ga InAs N Collector Ga InAs P Base InP N+ Emitter N+ N P N N P Conventional InP HBT technology 10um 1um

6 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Separate varactor layers Varactors and HBTs can be separately optimized. Varactor layers can be grown either above or underneath the transistor layers. Varactor layers underneath transistor layers complicate interconnect. Varactor layers above transistor layers require stepper technology.

7 Unclassified High Speed Electronics Group Faculty of Electrical Engineering InP Semi-insulating Substrate InP N+ Varactor Connect InP N Varactor N Ga InAs P Base InP N+ Sub-Collector InP N Collector Ga InAs P Base InP N+ Emitter N+ N P N P N InP HBT technology with Separate Varactor Layers

8 Unclassified High Speed Electronics Group Faculty of Electrical Engineering This Work Carried out by contact lithography-varactor layers underneath transistor layers. Wide tuning range Colpitts X band VCO demonstrated as first attempt. Simplified VBIC transistor model predicts well VCO’s performance.

9 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Transistor Properties Ft=180 GHz Fmax=200GHz Vturn-on=0.5V Vce-breakdown=5V Ic max (Vce=3v)=30mA β AC =50

10 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Transistor Modeling DC Measurements and s-parameters Small-signal equivalent circuit parameters extraction. Degenerate VBIC model with 18 parameters only

11 Unclassified High Speed Electronics Group Faculty of Electrical Engineering VBIC large signal model

12 Unclassified High Speed Electronics Group Faculty of Electrical Engineering VBIC model parameters extracted at specific bias, Does it work for large signal VCO modeling ?

13 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Varactor Design & Modeling We have compared 2 types of varactors: 1.Base-Collector layers. 2.Separate layers with N d =10 17 cm -3.

14 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Varactor Modeling Different size varactors, for scaleable model extraction. Semi-lumped model Rectangular varactors achieving 1 ohm series resistance.

15 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Varactor modeling Using simple model with text book equations.

16 Unclassified High Speed Electronics Group Faculty of Electrical Engineering VCO schematics – Colpitts configuration

17 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Full EM Simulation

18 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Testing VCO

19 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Comparison between Measurement and Simulation with degenerate VBIC model

20 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Measured phase noise

21 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Phase Noise Simulation Phase noise parameters extraction for VBIC model Kfn=1E-12 Afn=1

22 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Conclusions InP HBT X band VCO with separate varactor layers underneath transistor layers achieved tuning range of 12% and phase noise of -94dB/Hz at 100KHz. Future work: VCO layers on top of transistor layers for higher frequencies, and optoelectronic applications..

23 Unclassified High Speed Electronics Group Faculty of Electrical Engineering Acknowledgement We would like to thank ….. Dr. David Rosenfeld for supporting the project. Rafael Microelectronic Direcrotate Design groupe and Testing House. Technion Russell Berrie Nanotechnology Institute. Liron Arazi and Kochavi Shemuel for design and testing assistance. Dr. Asher Madjar.


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