1. Energy Delay Vdd = ? (Td,max, Emin) Vdd=? (Td,min, Emax) Vdd =? (Td, E) EE141 Project Phase 3 Group # Name 1, Name 2, Name 3 Key Results: LDPC Code Structure: Wire Estimation: Worst case length= Loading = Energy-Delay Curve

2. Poster Instructions Fill the content of previous cover slide; Replace this and later slides with your own materials; Since the poster board is 30”x40”, limit the number of slides to ≤12 (including the cover slide); While poster boards and mounting tools (glue, knife, ruler, etc.) will be provided at BWRC, you are responsible for printing the slides beforehand and for mounting them onto the board; BWRC will be open for poster preparation on Wednesday (May 5th) 12:00 pm.

3. Key Content Floorplan of your LDPC decoder Wire loading estimation Circuit topology and analysis Logic gate sizing Simulation results

4. Poster Session Format All team members are expected present during the time slot signed up; Each team will be given ~10 minutes to present the work and 3~5 minutes for Q&A; Grade will be based on completeness and accuracy of results, as well as quality of presentation.

5. Directions to BWRC http://bwrc.eecs.berkeley.edu/Background/directions.htm

6. Last but not least Remember to email your slides to ee141@cory.eecs.berkeley.edu ee141@cory.eecs.berkeley.edu by Wednesday (5/5) 12:00 pm!