Presentation is loading. Please wait.

Presentation is loading. Please wait.

VIIT-GRAPES Collaboration C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune.

Similar presentations


Presentation on theme: "VIIT-GRAPES Collaboration C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune."— Presentation transcript:

1 VIIT-GRAPES Collaboration C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune

2 VIIT-TIFR collaboration YearNo. of projects No. of BE students No. of faculty (VIIT) No. of scientists/ engineers (TIFR) Departments (VIIT) E&TC E&TC E& TC, Computer Engg E& TC, Computer Engg., IT E& TC, Computer Engg., IT

3 VIIT students in TIFR Sr. No.Name of student (Batch)Project at TIFRPostLab at TIFR 1Sanket Kamathe (2010) Silicon Photo Multiplier (SiPM) Jr. Research Fellow Solid State Electronics, Mumbai 2Ameya Deshpande (2010)Tera Hertz SpectroscopyJr. Research Fellow 3Raj Patil (2011)Plasmonics NRIM National Photonics Fellowship 4Aniket Patil (2011)Plasmonic Interconnects National Photonics Fellowship 5Harshad Surdi (2012)Tera Hertz SpectroscopyJr. Research Fellow 6Raghunandan Shukla (2011)SiPM, VLSI, Embedded High Energy Physics, Mumbai 7Sarrah Lokahandwala (2013)FPGA based systems, SiPMJr. Research Fellow 8Suraj Kolhe (2012)VLSI, EmbeddedJr. Research Fellow Cosmic Rays Laboratory, Ooty 9Serin V. John (2013)High voltage DAS, EmbeddedJr. Research Fellow

4 Software Projects Sr. No. 1Data management for Muon Detector Station 2Data Management for Scintillator Detector system 3Parallelization of Corsika 4Parallelization of G3SIM (C++ programme) 5Dynamic ROOT plotting

5 Hardware Projects Sr. No. Project 132-channel FPGA based counter with USB interface 264-channel FPGA based counter with ethernet interface 3FPGA based I2C communication 4High voltage Data acquisition system 5Solar PV 6High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier

6 32 Channel FPGA Based Counter Last year: 32 channel 24 bit high-speed counter implemented on a Actel FPGA (counter and digital logic part) FPGA and PIC micro-controller interfacing done Data logging to PC by a PIC micro-controller via USB protocol (Linux compatible)

7 32 Channel FPGA Based Counter This year: FPGA programming – VHDL to Verilog conversion is in progress (small Verilog programs (counter, etc.) implemented and tested on hardware) Pulse width measurement logic under development New counter logic development in Verilog is in progress

8 64 Channel FPGA Based Counter (Scalar) Last year: Simulations of 32 bit 64 channel counter 4 channel 16 bit Counter (Scalar) implementation on SPARTAN3E FPGA using VHDL Data transfer to PC through ARM7 controller, via Ethernet protocol (UDP/IP) demonstrated Multi-board configuration (IP Address based) with 2 ARM boards Multi-threading approach demonstrated for data reception on PC

9 64 Channel FPGA Based Counter (Scalar) This year: FPGA programming – VHDL to Verilog conversion is in progress 4 channel 4 bit counter demonstrated SPARTAN3E FPGA in Verilog Automated approach to toggle between 64 channels is demonstrated Multi-board configuration: synchronization of boards with I2C protocol demonstrated for 2 ARM Boards Time stamping with milliseconds accuracy is demonstrated Pulse width measurement logic under development Ethernet part : Data transfer with TCP/IP protocol is under development

10 High Voltage Data Acquisition System Last year: 48 channels system for PMT voltage monitoring developed 1 V resolution in 2500 V This system tested on actual PMT setup at CRL, Ooty Data logging via USB every 5 sec

11 Block diagram

12 High voltage monitoring

13 High Voltage Data Acquisition System This year: Different protection Circuits for already developed high voltage data acquisition board being developed and tested Temperature, Humidity etc. sensors being tested for inclusion in high voltage data acquisition board

14 Design and Implementation of Multiple Panels Solar Power System Last year: Maximum Power Point Tracking (MPPT) based charger developed for 25W solar panel Data logging system (Voltage, Current, Power) for a single solar panel developed (via USB protocol)

15 Design and Implementation of Multiple Panels Solar Power System This year: Improvement on MPPT charger circuit Inclusion of Buck-Boost converter for high efficiency Multiple Solar Panel Configuration with Data logging Different Protection Circuits inclusion Temperature Sensing

16 Design and Implementation of Multiple Panels Solar Power System This year:- Design of solar power system for 1kW of power with 4 solar panels and 8 batteries. Design of a Buck Boost Converter. Design of a Isolated Boost Converter. To design a Load Sharing System. Specifications of PV Panels :- V oc for each panel = 42V I sc for each panel = 7.6A V mpp for each panel= 35.25V I mpp for each panel=7.4A

17 I2C based multiple FPGA Configuration Started from this year Counter based projects uses FPGA, so in future a multiple FPGA configuration will be needed Multiple FPGA’s (slaves) will communicate to PIC based microcontroller (master) via I2C protocol PIC micro-controller to PC communication via USB is developed previously and used for various projects

18 High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier

19 Silicon Photo-Multiplier (SiPM) FIIG, University of Pisa, Italy

20 SiPM Biasing

21 Specifications of Power Supply ParametersValue Maximum Output Voltage100 V Output Voltage Resolution25 mV Output Channels16 Maximum Current Limit (Per Channel)100 uA Typical SiPM Temperature Compensation Coeff.50 mV/˚C Temperature Detection Resolution0.1 ˚C * Also, total power supply unit should be as small as possible.

22 Temperature Compensation Test First Passive Compensation is done for proof of principle SiPM typical temperature coeff. = 50 mV/˚C LM 35 temp. Coeff. = 10 mV/˚C A Circuit is connected to SiPM supply directly, that will change the supply voltage ground according to temperature SiPM

23 Test Setup for Compensation test SiPM Power Supply Compensation Circuit SiPM VME Test Setup PC Data logger for Temperature measurement Blower (Heat)

24 Results of Compensation Required Compensation is a non-linear Function

25 Block Diagram for Proposed Power Supply High Voltage Generation (Voltage Multiplier Chain) Control Unit (Micro-controller) Temperature Sensors Voltage Regulation Scheme PC USB SiPM Current Sense DAC

26 Test Board

27 Tests Performed DAC Stability Line Regulation Load Regulation Linearity Time Drift Capacitor for Noise elimination at output and stability

28 DAC Stability uV variation in 5 V

29 Line Regulation % for 10% change in line voltage 0.03% for 20% change in line voltage

30 Load Regulation No load to Full load (100uA) Best % Channel 2 Worst 1.55% Channel 8

31 Linearity

32 Time Drift (Channel 1) Supply Voltage Regulator Output

33 Time Drift Error Plots 600 mVp-p change100 mV change Supply Voltage Error PlotRegulator Output Error Plot

34 Ceramic Capacitor for reducing ripple

35 Time Drift (Improved) with 0.1  f Capacitor Without Capacitor With 0.1 uf Cap 15 mV Change Channel 1

36 Histograms

37 Comparison Between 0.1  f and 0.01  f

38 Histograms

39 Voltage Generation (Voltage Multiplier) A simple 10-stage Voltage multiplier chain is build with diodes (1N4148) and capacitors (0.22  F) The chain is tested for input frequencies 50 Hz to 5 MHz and for sine and square inputs.

40 Chain testing

41 Specifications achieved on test board ParametersRequired ValueAchieved Value Maximum Output Voltage100 V88.5 V with chain Output Voltage Resolution25 mV50 mV Output Channels168 Maximum Current Limit (Per Channel)100 uA Typical SiPM Temperature Compensation Coeff. 50 mV/˚C Temperature Resolution0.1 ˚C A stability of 10 mV in 50 mV resolution is achieved

42 Conclusions Software project: Except Parallelization of CORSIKA all other software projects have been partially implemented and are being fine tuned Hardware projects: 1.Standard PIC micro-controller based USB has been standardized 2.ARM7 based Ethernet - UDP implemented, TCP in advanced stage 3.FPGA – VHDL to Verilog transition made, 32 channel counter in advanced stage, 64 channel also in good shape, I2C in initial stage 4.High Voltage Monitoring – Advanced stage 5.Solar PV – R&D on Multiple panel, high power system optimization 6.SiPM power supply – In advanced stage

43 Guides from VIIT C S Garde - Coordinator V M Aranake M S Karyakarte S J Thaware K J Raut Mrs S Y Desai

44 Guides from TIFR S K Gupta - Coordinator S R Dugad Atul Jain Jagdeesan Mohanty Hariharan Raghunandan Sarah Serin Suraj

45 Students (Computer) 1.Mustafa Adib 2.Modak Ameya 3. Marathe Amogh 4. Rachit Kulshrestha 5. Shushupti Ajmire 6. Tejasvi Belsare 7. Dhawal Priyadarshi 8. Ms Devanshi Shah 9. Shubham Gupta 10. Irom Ajay Singh 11. Kishan Rao 12. Tejas Rao

46 Students (IT) 1.Qaidjohar Jawadwala 2.Harsh Kundnani 3.Dyaneshwar Kothule 4.Ms Shivangi Hiray 5.Ms Rekha Sangwan 6.Runa Ganeshan 7.Ayushi Tripathi 8.Ankit Bhavsar 9.Nikhil Mantri

47 Students (Electronics) 1.Aditya Godbole, Veronica D’Souza, Saumitra Kale 2.Akshay Manjare, Digvijay Tambhale, Shefali Rai 3.Afshan Shaikh, Akhil Kurup, Syed Shadab 4.Kamlesh Shinde, Bhagyashree Kalaskar, S Venkatesh 5.Ravi Prakash, Vinit Shah, Sanket Dahiwal 6. Jaydeep Kshirsagar, Kushal Kshirsagar 7.Pankaj Rakshe (ME)

48 Thank you

49 Work Plan TasksDuration Sophisticated Voltage Multiplier Chain BuildingNovember 2013 Temperature Compensation Algorithm implementation in micro- controller November 2013 Current Sensing ImplementationNovember 2013 Testing with Actual SiPM SetupDecember 2013 All modules-on-one-board PCB designDecember 2013 New Board testing and data analysisJanuary 2014

50 References [1] K.C. Ravindran, “Silicon Photo-multiplier development at GRAPES- 3”, WAPP workshop, CRL, Ooty. [2] Bajarang Sutar, “A talk on study of characteristics of SiPM”, TIFR, Mumbai. [3] R. Bencardino, J.E. Eberhardt, “Development of a Fast-Neutron Detector With Silicon Photomultiplier Readout”, IEEE Trans. On Nuclear Science, 2009

51 ERP system for Muon Detector Stations

52 Problem Statement Manufacturing of muon detector stations. Lack of integrated solutions Collaboration between departments Analysis and performance checking Inventory Management Ease of retrieval in data Management of manufacturing process and employees

53 Objectives To maintain and manage the data from production to construction stage of muon detector station To generate various reports To perform the analysis based on failure rate of component,user performance etc. Enhancing the operational efficiency of business resources.

54 What we have done until now ? Requirement Gathering Literature Survey Study about ERP system ER diagram Schema Diagram Proposed System Features Users and their roles

55 Literature Survey Software package that integrates all necessary business functions into a single system Features of ERP system-Componentized, Integrated, Flexible ERP follows three-tier architecture Application Layer Presentation Layer Database Layer

56 Literature Survey (Continued…) Functionalities Of ERP system Financial Management Human Resource Management Manufacturing Management Product Lifecycle Management Inventory Management Security

57 Literature Survey (Continued…)

58


Download ppt "VIIT-GRAPES Collaboration C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune."

Similar presentations


Ads by Google