Presentation on theme: "VIIT-GRAPES Collaboration"— Presentation transcript:
1VIIT-GRAPES Collaboration C S GardeVishwakarma Institute of Information Technology (VIIT),Pune
2VIIT-TIFR collaboration YearNo. of projectsNo. of BE studentsNo. of faculty (VIIT)No. of scientists/ engineers (TIFR)Departments (VIIT)12E&TC81971133915E& TC, Computer Engg.13381210E& TC, Computer Engg., IT1747
3VIIT students in TIFR Sr. No. Name of student (Batch) Project at TIFR PostLab at TIFR1Sanket Kamathe (2010)Silicon Photo Multiplier (SiPM)Jr. Research FellowSolid State Electronics, Mumbai2Ameya Deshpande (2010)Tera Hertz Spectroscopy3Raj Patil (2011)Plasmonics NRIMNational Photonics Fellowship4Aniket Patil (2011)Plasmonic Interconnects5Harshad Surdi (2012)6Raghunandan Shukla (2011)SiPM, VLSI, EmbeddedHigh Energy Physics, Mumbai7Sarrah Lokahandwala (2013)FPGA based systems, SiPM8Suraj Kolhe (2012)VLSI, EmbeddedCosmic Rays Laboratory, Ooty9Serin V. John (2013)High voltage DAS, Embedded
4Software Projects Sr. No. 1 Data management for Muon Detector Station 2Data Management for Scintillator Detector system3Parallelization of Corsika4Parallelization of G3SIM (C++ programme)5Dynamic ROOT plotting
5Hardware Projects Sr. No. Project 1 32-channel FPGA based counter with USB interface264-channel FPGA based counter with ethernet interface3FPGA based I2C communication4High voltage Data acquisition system5Solar PV6High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier
632 Channel FPGA Based Counter Last year:32 channel 24 bit high-speed counter implemented on a Actel FPGA (counter and digital logic part)FPGA and PIC micro-controller interfacing doneData logging to PC by a PIC micro-controller via USB protocol (Linux compatible)
732 Channel FPGA Based Counter This year:FPGA programming – VHDL to Verilog conversion is in progress (small Verilog programs (counter, etc.) implemented and tested on hardware)Pulse width measurement logic under developmentNew counter logic development in Verilog is in progress
864 Channel FPGA Based Counter (Scalar) Last year:Simulations of 32 bit 64 channel counter4 channel 16 bit Counter (Scalar) implementation on SPARTAN3E FPGA using VHDLData transfer to PC through ARM7 controller, via Ethernet protocol (UDP/IP) demonstratedMulti-board configuration (IP Address based) with 2 ARM boardsMulti-threading approach demonstrated for data reception on PC
964 Channel FPGA Based Counter (Scalar) This year:FPGA programming – VHDL to Verilog conversion is in progress4 channel 4 bit counter demonstrated SPARTAN3E FPGA in VerilogAutomated approach to toggle between 64 channels is demonstratedMulti-board configuration: synchronization of boards with I2C protocol demonstrated for 2 ARM BoardsTime stamping with milliseconds accuracy is demonstratedPulse width measurement logic under developmentEthernet part : Data transfer with TCP/IP protocol is under development
10High Voltage Data Acquisition System Last year:48 channels system for PMT voltage monitoring developed1 V resolution in 2500 VThis system tested on actual PMT setup at CRL, OotyData logging via USB every 5 sec
13High Voltage Data Acquisition System This year:Different protection Circuits for already developed high voltage data acquisition board being developed and testedTemperature, Humidity etc. sensors being tested for inclusion in high voltage data acquisition board
14Design and Implementation of Multiple Panels Solar Power System Last year:Maximum Power Point Tracking (MPPT) based charger developed for 25W solar panelData logging system (Voltage, Current, Power) for a single solar panel developed (via USB protocol)
15Design and Implementation of Multiple Panels Solar Power System This year:Improvement on MPPT charger circuitInclusion of Buck-Boost converter for high efficiencyMultiple Solar Panel Configuration with Data loggingDifferent Protection Circuits inclusionTemperature Sensing
16Design and Implementation of Multiple Panels Solar Power System This year:-Design of solar power system for 1kW of power with 4 solar panels and 8 batteries.Design of a Buck Boost Converter.Design of a Isolated Boost Converter.To design a Load Sharing System. Specifications of PV Panels :-Voc for each panel = 42VIsc for each panel = 7.6AVmpp for each panel= 35.25VImpp for each panel=7.4A
17I2C based multiple FPGA Configuration Started from this yearCounter based projects uses FPGA, so in future a multiple FPGA configuration will be neededMultiple FPGA’s (slaves) will communicate to PIC based microcontroller (master) via I2C protocolPIC micro-controller to PC communication via USB is developed previously and used for various projects
18High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier
19Silicon Photo-Multiplier (SiPM) Multi-pixel semiconductor Avalanchephotodiode.A Solid State DeviceOperating voltage (30-120V)Resolution - Single photon detectionResponse time – ~1 nsHigh gainHigh Quantum Efficiency – 90%High Photon Detection Efficiency – 60%SiPM Introduction in short.FIIG, University of Pisa, Italy
20SiPM BiasingGain is dependant on over voltage. When breakdown voltage changes due to temperature, the amount of over-voltage will change if supply voltage is constant.
21Specifications of Power Supply ParametersValueMaximum Output Voltage100 VOutput Voltage Resolution25 mVOutput Channels16Maximum Current Limit (Per Channel)100 uATypical SiPM Temperature Compensation Coeff.50 mV/˚CTemperature Detection Resolution0.1 ˚CSiPM size is small, so this unit should be close to SiPM and for mounting purpose it should be small.* Also, total power supply unit should be as small as possible.
22Temperature Compensation Test SiPMFirst Passive Compensation is done for proof of principleSiPM typical temperature coeff. = 50 mV/˚CLM 35 temp. Coeff. = 10 mV/˚CA Circuit is connected to SiPM supply directly, that will change the supply voltage ground according to temperatureBut, does compensation really works?To find out this, a small exercise is done by adding passive compensation to SiPM power supply.
23Test Setup for Compensation test SiPM PowerSupplyCompensationCircuitSiPM VMETest SetupData logger forTemperaturemeasurementBlower(Heat)The circuit is connected in actual setup of SiPM.The Setup is heated and allowed to cool while checking the gain.PC
24Results of Compensation Required Compensation isa non-linear Function
25Block Diagram for Proposed Power Supply High Voltage Generation (Voltage Multiplier Chain)PCUSBControl Unit (Micro-controller)Voltage Regulation SchemeTemperature SensorsDACCurrent SenseSiPM
39Voltage Generation (Voltage Multiplier) A simple 10-stage Voltage multiplier chain is build with diodes (1N4148) and capacitors (0.22 F)The chain is tested for input frequencies 50 Hz to 5 MHz and for sine and square inputs.
41Specifications achieved on test board ParametersRequired ValueAchieved ValueMaximum Output Voltage100 V88.5 V with chainOutput Voltage Resolution25 mV50 mVOutput Channels168Maximum Current Limit (Per Channel)100 uATypical SiPM Temperature Compensation Coeff.50 mV/˚CTemperature Resolution0.1 ˚CA stability of 10 mV in 50 mV resolution is achieved
42Conclusions Software project: Except Parallelization of CORSIKA all other software projects have been partially implemented and are being fine tunedHardware projects:Standard PIC micro-controller based USB has been standardizedARM7 based Ethernet - UDP implemented, TCP in advanced stageFPGA – VHDL to Verilog transition made, 32 channel counter in advanced stage, 64 channel also in good shape, I2C in initial stageHigh Voltage Monitoring – Advanced stageSolar PV – R&D on Multiple panel, high power system optimizationSiPM power supply – In advanced stage
43Guides from VIIT C S Garde - Coordinator V M Aranake M S Karyakarte S J ThawareK J RautMrs S Y Desai
44Guides from TIFR S K Gupta - Coordinator S R Dugad Atul Jain Jagdeesan MohantyHariharanRaghunandanSarahSerinSuraj
45Students (Computer) Mustafa Adib Modak Ameya Marathe Amogh Rachit KulshresthaShushupti AjmireTejasvi BelsareDhawal PriyadarshiMs Devanshi ShahShubham GuptaIrom Ajay SinghKishan RaoTejas Rao
49Work Plan Tasks Duration Sophisticated Voltage Multiplier Chain BuildingNovember 2013Temperature Compensation Algorithm implementation in micro-controllerCurrent Sensing ImplementationTesting with Actual SiPM SetupDecember 2013All modules-on-one-board PCB designNew Board testing and data analysisJanuary 2014
50References K.C. Ravindran, “Silicon Photo-multiplier development at GRAPES- 3”, WAPP workshop, CRL, Ooty.  Bajarang Sutar, “A talk on study of characteristics of SiPM”, TIFR, Mumbai.  R. Bencardino, J.E. Eberhardt, “Development of a Fast-Neutron Detector With Silicon Photomultiplier Readout”, IEEE Trans. On Nuclear Science, 2009
52Problem Statement Manufacturing of muon detector stations. Lack of integrated solutionsCollaboration between departmentsAnalysis and performance checkingInventory ManagementEase of retrieval in dataManagement of manufacturing process and employees
53ObjectivesTo maintain and manage the data from production to construction stage of muon detector stationTo generate various reportsTo perform the analysis based on failure rate of component ,user performance etc.Enhancing the operational efficiency of business resources.
54What we have done until now ? Requirement GatheringLiterature SurveyStudy about ERP systemER diagramSchema DiagramProposed SystemFeaturesUsers and their roles
55Literature SurveySoftware package that integrates all necessary business functions into a single systemFeatures of ERP system-Componentized, Integrated, FlexibleERP follows three-tier architectureApplication LayerPresentation LayerDatabase Layer