Presentation on theme: "A. Lai 30/31 Jan 2002 DIALOG CARIOCACARIOCA ?. A. Lai 30/31 Jan 2002 DIALOG DIALOG- (Nov 2001) has 83 pins on a PGA100 package (~13x13 mm 2 ) DIALOG-"— Presentation transcript:
A. Lai 30/31 Jan 2002 DIALOG CARIOCACARIOCA ?
A. Lai 30/31 Jan 2002 DIALOG DIALOG- (Nov 2001) has 83 pins on a PGA100 package (~13x13 mm 2 ) DIALOG- (April 2002) will have 75 (min) to 91 (max) pins PGA100 or QFP100 (14x14 mm 2 ) The layout is strongly pad limited Connections to/from ASD: 16 LVDS in (32 pins) 2 Discriminator threshold lines 2 Test pulse (4 pins) tot 38 pins (reducible to 22 if non differential inputs are used) 16 LVDS input Prog. Delayer Prog. Dig. Shaper MASKMASK Logical Channel Generation 8 LVDS output I 2 C Interface SCL SDA DIALOG Configuration registers DLL Address 16 bits Rate counter CKext Tst Pls0 Pls1 ASD pulse generation DIALOG- functional scheme
A. Lai 30/31 Jan 2002 DIALOG-CARIOCA Same board. How to assemble DIALOG and CARIOCA on F/E? - Mechanical integration is not trivial (an additional board will be needed ?!) Same technology Integrate the two chips on the same die and put one single IC on front- end ? + (On top) (…Otherwise)
A. Lai 30/31 Jan 2002 Consequences (1) 1.New schematics and layout technically feasible and relatively easy 2. Who is going to do it? Manpower… (Cagliari can) 3. Possible “interference/incompatibility” problems in integration? DIALOG “uses” a 100 kHz clock (during data/configuration transfer). It behaves like a silent quasi-analog device. The most dangerous (noisy) part are the current absorbing LVDS drivers Accurate layout can well separate this part from the analogue one (see below) Beside that, the “interaction” between the two parts is stronger at the board level (connections, mechanics, grounding…)
A. Lai 30/31 Jan 2002 Layout issues 250 m Std cells area: squeezable at least to 50% datapath Input signals Outputs (logical channels) controls
A. Lai 30/31 Jan m 61 m 290 m 2000 m 250 m Sizes of full custom cells Calibration DLL Prog. Delay, Digital Shaper and 1 st stage of logics (1 channel) Prog. Delay, Digital Shaper and 1 st stage of logics (8 channels)
A. Lai 30/31 Jan 2002 DIALOG-CARIOCA Geometrical layout Digital PWR/GND pins Analogue PWR/GND pins Analogue I/O Digital I/O Analogue PWR lines Digital PWR lines Standard Cells area ASD Delay and Digital Shaper Calibration DLL DAC Signals from chamber Logical channels (LVDS out) Digital controls
A. Lai 30/31 Jan 2002 SignalTypeCommentsSignalTypeComments P[15:0] (32) LVDS in 16 Physical signals; from ASD’s L[7:0] (16)LVDS outLogical signals; to ODE Tin (2)LVDS inTest signal; from SBS[1:0] (4)LVDS outPulse signals; to ASD’s Tout (2)LVDS outTest signal to next DIALOGVth1V level outDiscriminator threshold 1 SCin (2)LVDS inI 2 C clock inVth 2V level outDiscriminator threshold 2 SCout (2)LVDS outI 2 C clock outGRinInGlobal Reset SDin (2)LVDS inI 2 C data inGRoutoutGR to next DIALOG SDout (2)LVDSoutI 2 C data outA[6:0]InDevice Address GND/PWRSupply6 couples DIALOG&CARIOCA pinout: 69 pins 80 pins LQFP (10x10 mm 2 ), 80 or 100 pins (if pins are added) DIALOG- pinout (preliminary): 87 pins 100 pins LQFP, 14x14 mm 2 SignalTypeCommentsSignalTypeComments S[15:0]Analogue 16 analogue signals from chamber L[7:0] (16)LVDS outLogical signals; to ODE Tin (2)LVDS inTest signal; from SBGRinInGlobal Reset Tout (2)LVDS outTest signal to next DIALOGGRoutoutGR to next DIALOG SCin (2)LVDS inI 2 C clock inA[6:0]InDevice Address SCout (2)LVDS outI 2 C clock outGND/PWRSupply8 couples SDin (2)LVDS inI 2 C data in SDout (2)LVDSoutI 2 C data out
A. Lai 30/31 Jan 2002 From chamber FRONT-END BOARDS (my present envisaging) F/E boards inside chamber (not visible in reality) Chamber cageConnectors are accessible from outside DIALOGCARIOCA Logical channels out Controls out Controls inPWR/GND Logical channels out Controls out Controls inPWR/GND DIALOG – CARIOCA (separated) Interboard connections ?
A. Lai 30/31 Jan 2002 Consequences (2) 4. Additional time in the schedule. What is the present schedule? Chamber production starts beginning of 2003 The electronics to be used in the tests of produced chambers will not be the definitive one. Only the ASD chips will be used. This disentangles the front-end production schedule from the chamber production one. Proposal: Produce and test accurately both the final version of CARIOCA and DIALOG within 2002 (see “full chain test”). Prepare and submit the CARIOCA_DIALOG integrated version beginning of Test, compare and approve/discard it within half 2003.
A. Lai 30/31 Jan 2002 Consequences (3) 5. Impact on the system: The front-end design is simplified… but: We have MANY font-ends: Positive Negative RPC? GEM? Moreover: also a standalone CARIOCA (and DIALOG) version is needed How about RPC and GEM? Can they use the same chip as the MWPC? (This should be answered quickly…) Yes: 2 kinds of D-C chip are needed: DC+, DC-. No: 3 kinds: DC+, DC-, D/C standalone Still worthwhile ? We think yes: The cost is invariant with the number of project per wafer. DIALOG and CARIOCA will be developed and tested separately in any case
A. Lai 30/31 Jan 2002 Consequences (4) Which name? SuperDIALOG ? CARIOCAgliari ? SuperD ? A committee, a competition and a prize to solve this fundamental problem…
A. Lai 30/31 Jan 2002 Conclusions The CARIOCA-DIALOG integration is appealing from the system point of view and technically feasible. The impact on the Muon Project schedule can be minimized Differences with the standalone solution: On board connections, mechanics, grounding are better; Interaction with the LVDS drivers can be kept under control; Final answer can be given only by tests; The different kind of front-ends in the system are not a serious problem (the system cost is unaffected, the additional work is acceptable) A try is feasible and worthwhile The final decision could be postponed to the 1 st half of 2003, but the final versions of both CARIOCA and DIALOG should be realized with an eye to their integration (especially from the layout point of view).