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© Copyright 2014 Xilinx. Zynq intr – part 3. © Copyright 2014 Xilinx. Description of the effects on interrupt mapping when migrating a project from a.

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Presentation on theme: "© Copyright 2014 Xilinx. Zynq intr – part 3. © Copyright 2014 Xilinx. Description of the effects on interrupt mapping when migrating a project from a."— Presentation transcript:

1 © Copyright 2014 Xilinx. Zynq intr – part 3

2 © Copyright 2014 Xilinx. Description of the effects on interrupt mapping when migrating a project from a Vivado 2013.x project to a Vivado x project. Description of the special case for a single interrupt mapping Content

3 © Copyright 2014 Xilinx. Special cases Migrating a project from to 2014.x Let’s take a project used in and migrate it to

4 © Copyright 2014 Xilinx. The upgrade process The IP upgrade is automated by Vivado. The Concat block gets updated to the latest version in 2014.x The PS7 block gets updated to the latest version in 2014.x

5 © Copyright 2014 Xilinx. Upgrade from 2013.x to 2014.x Concat block The IP upgrade means a change of order for the interrupts compared to the order in 2013.x Concat in 2013.xConcat in 2014.x

6 © Copyright 2014 Xilinx. Let’s look at the parameter value for a project that was migrated from 2013.x to 2014.x: The parameter value is now “REVERSE”. Upgrade from 2013.x to 2014.x IRQ_F2P_MODE parameter

7 © Copyright 2014 Xilinx. Upgrade from 2013.x to 2014.x Generated PS7 source file internal interrupt vector As a result of the IRQ_F2P_MODE parameter value being “REVERSE”, the internal irq_f2p_i vector is now representing the mapping from 2013.x:

8 © Copyright 2014 Xilinx. Upgrade from 2013.x to 2014.x

9 © Copyright 2014 Xilinx. To keep the 2013.x original interrupt mapping it is necessary to reverse the input interrupt order on the concat block. The “REVERSE” parameter then takes care of arranging the mapping as was previously implemented in 2013.x. Conclusion for an upgrade

10 © Copyright 2014 Xilinx. Test Design Let’s remove the concat block and use a single interrupt:

11 © Copyright 2014 Xilinx. As there is no concat block involved it is a straight-forward mapping. The PS7 code is as previously seen: In0 is mapped to ID x

12 © Copyright 2014 Xilinx. The IRQ_F2P_MODE parameter from the PS7 source file is set to “DIRECT”. In0 is therefore mapped to ID x

13 © Copyright 2014 Xilinx. In 2014.x

14 © Copyright 2014 Xilinx. The PS7 parameter IRQ_F2P_MODE is now set to “REVERSE”: Migrating the project form 2013.x to 2014.x

15 © Copyright 2014 Xilinx. Upgrade from 2013.x to 2014.x Generated PS7 source file internal interrupt vector As a result of the IRQ_F2P_MODE parameter value being “REVERSE”, the internal irq_f2p_i vector is now representing the mapping from 2013.x:

16 © Copyright 2014 Xilinx. In0 mapping did not change compared to the implementation in 2013.x because the IRQ_F2P_MODE parameter was set to “REVERSE”. Upgrade from 2013.x to 2014.x

17 © Copyright 2014 Xilinx. Follow Xilinx facebook.com/XilinxInctwitter.com/XilinxIncyoutube.com/XilinxInc


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