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Virtex II Pro based SoPC design Part 2 Advanced. Before we start … The guidance consists of two parts: The guidance consists of two parts: Introduction.

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Presentation on theme: "Virtex II Pro based SoPC design Part 2 Advanced. Before we start … The guidance consists of two parts: The guidance consists of two parts: Introduction."— Presentation transcript:

1 Virtex II Pro based SoPC design Part 2 Advanced

2 Before we start … The guidance consists of two parts: The guidance consists of two parts: Introduction Introduction SoPC concept SoPC concept Working platforms Working platforms Design Flow – building basic system Design Flow – building basic system Advanced topics Advanced topics Adding user cores Adding user cores JTAG JTAG Debug Debug Simulation Simulation Demonstration Demonstration Today

3 Outline SoPC architecture – review SoPC architecture – review PLB bus PLB bus OPB bus OPB bus Adding user cores Adding user cores Adding cores without a bus Adding cores without a bus IPIF architecture IPIF architecture Adding cores to OPB and PLB buses Adding cores to OPB and PLB buses JTAG port JTAG port Hardware and Software debug Hardware and Software debug Hardware debugger – Chip Scope Pro Hardware debugger – Chip Scope Pro Software debugger – XMD Software debugger – XMD Demonstration Demonstration

4 SoPC architecture Processor Local Bus (PLB) 32-bit address, 64-bit data Separate read and write buses High performance Low load On-Chip peripheral bus (OPB) 32-bit address, 32-bit data Max peripherals High load Device Control Register bus (DCR) 32-bit transfer to and from GPR Direct accessible by PPC

5 PLB bus 64 bit data / 32 bit address configuration Up to 16 masters and slaves Decoupled address, read data, and write data buses Concurrent read and write transfer Address pipelining that reduces bus latency by overlapping a new write request with an ongoing write transfer and up to three read requests with an ongoing read transfer Four priority levels for master requests Byte-enable capability, supporting unaligned transfers

6 PLB bus architecture Each master has its own data read, write and address bus (all merged to wide buses) All slaves have shared write data and address bus Each slave has its own read data bus All slaves’ read data buses are merged to one wide bus (OR instead of merge in IBM implementation)

7 PLB bus master attachment PLB arbiter PLB Master [n] Arbitration signals M_BE [n*8:n*8+7] M_ABus [n*32:n*32+31] M_wrDBus [n*64:n*64+63] PLB_MRdDBus [n*64:n*64+63] Naming conventions: Naming conventions: Each signal from arbiter to master starts from “ PLB ” Each signal from arbiter to master starts from “ PLB ” Each signal from master to arbiter starts from “ M ” Each signal from master to arbiter starts from “ M ”

8 PLB bus slave attachment PLB arbiter PLB Slave [m] PLB_ABus [0:31] PLB_wrDBUS [0:63] Sl_rdDBus [m*64:m*64+63] Naming conventions: Naming conventions: Each signal from arbiter to slave starts from “ PLB ” Each signal from arbiter to slave starts from “ PLB ” Each signal from slave to arbiter starts from “ Sl ” Each signal from slave to arbiter starts from “ Sl ”

9 OPB bus Actually, AND-OR interconnect structure (distributed multiplexer) bit data / bit address configuration Bus arbitration overlapped with last cycle of bus transfers 16 masters and unlimited number of slaves 8-64-bit slaves and bit masters Dynamic bus sizing: byte, halfword, fullword, and doubleword transfers Optional Byte Enable support Single cycle transfer of data between OPB bus master and OPB slaves

10 OPB bus architecture Each master has its own read data and address bus (all ORed to single buses) Each slave has its own read data bus (all ORed with masters’ read data bases to single bus) ORed masters’ and slaves’ data buses represents shared OPB write data bus OPB_DBus

11 OPB bus master attachment OPB bus logic OPB Master [n] Mn_BE [0:7] Mn_DBus [0:63] Mn_ABus [0:31] OPB_DBus [0:63] Naming conventions: Naming conventions: Each signal from bus logic to master starts from “ OPB ” Each signal from bus logic to master starts from “ OPB ” Each signal from master to bus logic starts from “ Mn ” Each signal from master to bus logic starts from “ Mn ”

12 OPB bus slave attachment OPB bus logic OPB Slave [m] OPB_ABus [0:31] Sln_DBUS [0:63] OPB_DBus [0:63] Naming conventions: Naming conventions: Each signal from bus logic to slave starts from “ OPB ” Each signal from bus logic to slave starts from “ OPB ” Each signal from slave to bus logic starts from “ Sln ” Each signal from slave to bus logic starts from “ Sln ”

13 Adding user logic to design Choose chip with required hard cores inside Add required soft cores Add user logic Question: How user logic is added to design? Answer : user cores creation  E E E EDK can only recognize logic organized in a form of core

14 User core directory structure Project root directory pcores datadevlhdlnetlistdoc Optional vhdlverilog “ mpd ” file “ pao ” file “ bbd ” file Usually this directory structure is created automatically by “ Import peripheral Wizard ” !

15 User core directory structure Data directory contains EDK interface files for the core: Data directory contains EDK interface files for the core: “ mpd ” file – Microprocessor Peripheral Description “ mpd ” file – Microprocessor Peripheral Description “ pao ” file – Peripheral Analyze Order “ pao ” file – Peripheral Analyze Order “ bbd ” file – Black Box Definition “ bbd ” file – Black Box Definition HDL directory contains HDL (VHDL or Verilog) files representing the core HDL directory contains HDL (VHDL or Verilog) files representing the core Netlist directory contains synthesized netlists added as a part of core (not always all the core is written in HDL) Netlist directory contains synthesized netlists added as a part of core (not always all the core is written in HDL) Doc directory contains documentation of the peripheral Doc directory contains documentation of the peripheral Devl directory contains different files created by “ Import Peripheral Wizard ” Devl directory contains different files created by “ Import Peripheral Wizard ” Press to see example Press to see example Press to see example Press to see example Press to see example Press to see example

16 MPD file MPD file defines the interface of the peripheral MPD file defines the interface of the peripheral MPD includes: MPD includes: List of ports and default connectivity for bus interfaces List of ports and default connectivity for bus interfaces List of parameters and default values List of parameters and default values Any MPD parameter is overwritten by the equivalent MHS assignment Any MPD parameter is overwritten by the equivalent MHS assignment

17 MPD file - example BEGIN opb_gpio ## Peripheral Options OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION SIM_MODELS = BEHAVIORAL:STRUCTURAL ## Bus Interfaces BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE ## Generics for VHDL or Parameters for Verilog PARAMETER C_BASEADDR=0xFFFFFFFF, DT=std_logic_vector, MIN_SIZE=0x100, BUS=SOPB PARAMETER C_HIGHADDR=0x , DT = std_logic_vector, BUS=SOPB PARAMETER C_OPB_DWIDTH=32, DT=integer, BUS=SOPB PARAMETER C_OPB_AWIDTH=32, DT=integer, BUS=SOPB PARAMETER C_GPIO_WIDTH=32, DT=integer PARAMETER C_ALL_INPUTS=0, DT=integer ## Ports PORT OPB_Clk = “”, DIR=IN, SIGIS=CLK, BUS=SOPB PORT OPB_Rst = OPB_Rst, DIR=IN, BUS=SOPB PORT OPB_ABus = OPB_ABus, DIR=IN, VEC=[0:C_OPB_AWIDTH-1], BUS=SOPB PORT OPB_BE = OPB_BE, DIR=IN, VEC=[0:C_OPB_DWIDTH/8-1], BUS=SOPB PORT OPB_DBus = OPB_DBus, DIR=IN, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPB PORT OPB_RNW = OPB_RNW, DIR=IN, BUS=SOPB PORT OPB_select = OPB_select, DIR=IN, BUS=SOPB PORT OPB_seqAddr = OPB_seqAddr, DIR=IN, BUS=SOPB PORT GPIO_DBus = Sl_DBus, DIR=OUT, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPB PORT GPIO_errAck = Sl_errAck, DIR = OUT, BUS=SOPB PORT GPIO_retry = Sl_retry, DIR = OUT, BUS=SOPB PORT GPIO_toutSup = Sl_toutSup, DIR=OUT, BUS=SOPB PORT GPIO_xferAck = Sl_xferAck, DIR=OUT, BUS=SOPB PORT GPIO_IO = “”, DIR=INOUT, VEC=[0:C_GPIO_WIDTH-1], ENABLE=MULT END

18 PAO file A PAO file contains a list of HDL files that are needed for synthesis, and defines the analyze order for compilation A PAO file contains a list of HDL files that are needed for synthesis, and defines the analyze order for compilation Following format is used in PAO: Following format is used in PAO: lib library hdl_file_basename Library specifies the unique library for the peripheral, and HDL file names are specified without a file extension All names are in lower-case Usually, library version is also specified

19 PAO file - example lib common_v1_00_a common_types_pkg lib common_v1_00_a pselect lib opb_gpio_v1_00_a gpio_core lib opb_gpio_v1_00_a opb_gpio

20 BBD file The BBD file manages the file locations of optimized hardware netlists for the black-box sections of the design The BBD format is a look-up table chart that lists netlist files The first line is the header of the look-up table The last column of the table must be the FILES column Each file is listed with the file extension of the hardware implementation netlist

21 BBD file - example C_FAMILY C_BUS_CONFIG FILES virtex 1 virtex/ip1.edf virtex 2 virtex/ip2.edf spartan2 1 virtex/ip1.edf spartan2 2 virtex/ip2.edf virtexe 1 virtex/ip1.edf virtexe 2 virtex/ip2.edf spartan2e 1 virtex/ip1.edf spartan2e 2 virtex/ip2.edf virtex2 1 virtex2/ip1.edf virtex2 2 virtex2/ip2.edf virtex2p 1 virtex2/ip1.edf virtex2p 2 virtex2/ip2.edf

22 Adding user logic Standalone core Master / slave bus core OPB slave PLB master- slave PLB slave

23 Bus core architecture To simplify the process of attaching a user core to a CoreConnect bus, the user core can make use of a portable, predesigned bus interface (called the IP Interface, IPIF) that takes care of the bus interface signals, bus protocol, and other interface issues The IPIF presents an interface to the user logic called the IP InterConnect (IPIC) User logic is designed with an IPIC interface to make use of the IPIF bus attachment and other services User logic that is designed with an IPIC has the advantage that it is portable and can be easily reused on different processor buses by changing the IPIF to which it is attached

24 3 methods of adding user logic Other logic added to FPGA via external tool (for example, ISE) IPIC ports are defined as external in embedded system User core fully added to embedded system This method is preferred

25 OPB IPIF architecture Optional features are marked in red

26 PLB IPIF architecture

27 Main IPIC signals – slave interface Bus2IP_Addr – address bus from the IPIF to the user logic (the same width as host address bus) Bus2IP_Addr – address bus from the IPIF to the user logic (the same width as host address bus) Bus2IP_BE – a bus of BE qualifiers from the IPIF to user logic. A bit in the. Bus2IP_BE set to ‘ 1 ’ indicates that the associated byte lane contains valid data Bus2IP_BE – a bus of BE qualifiers from the IPIF to user logic. A bit in the. Bus2IP_BE set to ‘ 1 ’ indicates that the associated byte lane contains valid data Bus2IP_Clk – clock input to the user logic (same as OPB_clk or PLB_clk) Bus2IP_Clk – clock input to the user logic (same as OPB_clk or PLB_clk) Bus2IP_CS – a bus of chip select signals from IPIF to user logic. It indicates a decode within a block of addresses (address space) Bus2IP_CS – a bus of chip select signals from IPIF to user logic. It indicates a decode within a block of addresses (address space) Bus2IP_CE - a bus of chip enable signals from IPIF to user logic. Indicates a decode of a particular register or address within the block of addresses Bus2IP_CE - a bus of chip enable signals from IPIF to user logic. Indicates a decode of a particular register or address within the block of addresses Bus2IP_RdCE – the same as Bus2IP_CE during read transaction Bus2IP_RdCE – the same as Bus2IP_CE during read transaction Bus2IP_WrCE – the same as Bus2IP_CE during write transaction Bus2IP_WrCE – the same as Bus2IP_CE during write transaction Bus2IP_Data - this is the data bus from the IPIF to the user logic; it is used for both master and slave transactions (the same width as the host bus data bus) Bus2IP_Data - this is the data bus from the IPIF to the user logic; it is used for both master and slave transactions (the same width as the host bus data bus) Bus2IP_RNW - indicates the transaction type (read or write). Bus2IP_RNW = 1 indicates a read transaction and Bus2IP_RNW = 0 indicates a write transaction. Bus2IP_RNW - indicates the transaction type (read or write). Bus2IP_RNW = 1 indicates a read transaction and Bus2IP_RNW = 0 indicates a write transaction. Bus2IP_Burst – this signal from the IPIF to the user logic indicates that the current transaction is a burst transaction Bus2IP_Burst – this signal from the IPIF to the user logic indicates that the current transaction is a burst transaction

28 Main IPIC signals – slave interface (2) IP2Bus_Ack (OPB), IP2Bus_RdAck, IP2Bus_WrAck (PLB) - These signals provide the read/write acknowledgement from the user logic to the IPIF. For writes, it indicates the data has been taken by the user logic. For reads, it indicates that valid data is available IP2Bus_Data - this is the data bus from the IPIF to the user logic; it is used for both master and slave transactions (the same width as the host bus data bus) IP2Bus_Error - this signal from the user logic to the IPIF indicates an error has occurred during the current transaction. It is valid when IP2Bus_Ack is asserted. IP2Bus_Intr (OPB), IP2Bus_IntrEvent (PLB) - output from the user logic to the IPIF that consists of interrupt event signals to be detected and latched inside the IPIF. IP2Bus_Retry - response from the user logic to the IPIF that indicates the currently requested transaction cannot be completed at this time and that the requesting master should retry the operation IP2Bus_ToutSup – this signal must be asserted by the user logic whenever its acknowledgement or retry response will take longer than 8 clock cycles.

29 Slave read – transaction example

30 Main IPIC signals – master interface Bus2IP_MstError - signal from the IPIF to the user logic indicates whether the transfer has an error Bus2IP_MstLastAck - a one-cycle acknowledgement of a master transaction from the IPIF to the user logic. A transaction may consist of multiple transfers (burst transaction); Bus2IP_MstLastAck will always accompany the last Bus2IP_MstAck for the transaction. Bus2IP_MstAck (OPB), Bus2IP_MstRdAck, Bus2IP_MstWrAck (PLB) - a one-cycle acknowledgement of a master transfer from the IPIF to the user logic. For writes it indicates that the IPIF has accepted the current data and is ready for the next data; for reads it indicates that valid data is present on the Bus2IP_Data bus. Bus2IP_MstRetry - a one-cycle alternative completion signal to Bus2IP_MstLastAck. It indicates that the requested transaction could not be performed but may succeed if retried; Bus2IP_MstTimeOut - (from the IPIF to the user logic) is a one- cycle alternative completion signal to Bus2IP_MstLastAck. It indicates that the requested transaction could not be performed within the timeout interval associated with the host bus.

31 Main IPIC signals – master interface (2) IP2Bus_Addr - an output from the user logic to the IPIF. It is the address bus for the current master transaction. It is valid when IP2Bus_Req is active. IP2Bus_MstBE - a bus of Byte Enables qualifiers from the user logic to the IPIF for a master transaction. A bit in the IP2Bus_MstBE set to ‘ 1 ’ indicates that the associated byte lane contains valid data IP2Bus_MstBurst qualifier from the user logic to the IPIC indicates the master transaction is a burst operation. IP2Bus_MstBusLock qualifier from the user logic to the IPIC indicates the master is requesting that the host bus be locked until IP2Bus_MstBusLock is deasserted IP2Bus_MstNum (OPB Only) - indicates the burst length for burst transfers. The number of transfers for the burst is IP2Bus_MstNum+1, so that a value of 0000 indicates a burst length of one, and a value of 1111 indicates a burst length of 16 IP2Bus_MstReq (OPB Only) - this signal from the user logic to the IPIF indicates that the user logic is requesting a master transaction IP2Bus_MstRNW(OPB Only) - an input to the IPIF from the user logic that indicates the transaction type (read or write). IP2Bus_MstRNW = 1 indicates a read transaction and IP2Bus_MstRNW = 0 indicates a write transaction IP2Bus_MstRdReq, IP2Bus_MstWrReq(PLB Only) - inputs to the IPIF from the user logic that indicates that the user logic is requesting a master transaction (read or write) IP2IP_Addr - an output from the user logic that indicates the local device address for the master transaction. This address will be the source for a master write transaction and the sink for a master read transaction

32 Master read – transaction example

33 Adding cores using “ Import peripheral Wizard …”

34 Creates templates with required bus interface Creates templates with required bus interface User logic has to be implemented later User logic has to be implemented later Imports fully implemented peripheral Imports fully implemented peripheral Peripheral need to have ports and parameters that conform to the conventions required by EDK Peripheral need to have ports and parameters that conform to the conventions required by EDK

35 Creating templates for new core Shared directory, peripheral stored there can be used by multiple projects Peripheral can be used only by current project

36 Creating templates for new core Version management Name of the peripheral must be the same as the name of the top- level entity

37 Creating templates for new core PLB slave and master-slave interfaces are supported PLB slave and master-slave interfaces are supported OPB slave only interface is supported OPB slave only interface is supported Choose required core components Choose required core components For each component chosen, additional windows will open for configuration For each component chosen, additional windows will open for configuration

38 Creating templates for new core According to chosen components, some signals are already connected According to chosen components, some signals are already connected Additional signals can be connected if needed Additional signals can be connected if needed

39 Importing existing peripheral Shared directory, peripheral stored there can be used by multiple projects Peripheral can be used only by current project

40 Importing existing peripheral Version management Name of the peripheral must be the same as the name of the top- level entity

41 Importing existing peripheral Three types of files can be added:

42 Importing existing peripheral MPD and PAO files are created during importing core. Existing MPD and PAO can be used MPD and PAO files are created during importing core. Existing MPD and PAO can be used

43 Importing existing peripheral In this stage, syntax of HDL code and library dependencies are checked. Error messages can be reported

44 Importing existing peripheral Bus interface has to be already implemented in imported peripheral Bus interface has to be already implemented in imported peripheral MicroBlaze only Power PC only If the names of user core ports follow IPIC standard names, they are connected automatically If the names of user core ports follow IPIC standard names, they are connected automatically Else, they have to be indicated explicitly Else, they have to be indicated explicitly

45 Importing existing peripheral Interrupt ports have to indicated to give possibility to connect them later to interrupt controller

46 Importing existing peripheral Defining peripheral parameters (attributes) and port parameters …

47 Importing existing peripheral

48 Summary: Logical library: abcd_v1_00_a Logical library: abcd_v1_00_a Version: 1.00.a Version: 1.00.a Bus interface(s): None Bus interface(s): None The following sub-directories will be created in the pcores repository in your project: - abcd_v1_00_a\data - abcd_v1_00_a\hdl - abcd_v1_00_a\hdl\vhdl - abcd_v1_00_a\netlist The following HDL source files will be copied into the abcd_v1_00_a\hdl\vhdl directory: - my_abcd.vhd The following files will be created under the abcd_v1_00_a\data directory: - abcd_v2_1_0.mpd - abcd_v2_1_0.pao - abcd_v2_1_0.bbd The following netlist files will be copied into the abcd_v1_00_a\netlist directory: - my_fifo.edn Thank you for using this Import Peripheral Wizard!

49 Adding new core to the project

50 Intro to JTAG

51 What is JTAG ? Joint Joint Test Test Action Action Group Group JTAG is IEEE 1149 standard JTAG is IEEE 1149 standard This standard defines 5-pin serial protocol for accessing and controlling signal-levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself This standard defines 5-pin serial protocol for accessing and controlling signal-levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself Appendix B

52 JTAG architecture C0C1C2C3C4 Boundary scan register (BSR) BSR read and write operations take place at the same time, in serial fashion, with the new value shifted in from TDI, while the previous value is shifted out from TDO BSR read and write operations take place at the same time, in serial fashion, with the new value shifted in from TDI, while the previous value is shifted out from TDO C0 and C3 are input cells C0 and C3 are input cells C1 and C4 are output cells C1 and C4 are output cells C2 is enable cell C2 is enable cell O I BI Appendix B

53 JTAG interface signals TRST is the Test-ReSeT input which initializes and disables the test interface TRST is the Test-ReSeT input which initializes and disables the test interface TCK is the Test-ClocK input which controls the timing of the test independently from any system clocks. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency up to one half of the PowerPC core clock TCK is the Test-ClocK input which controls the timing of the test independently from any system clocks. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency up to one half of the PowerPC core clock TMS is the Test Mode Select input which controls the transitions of the test interface state machine TMS is the Test Mode Select input which controls the transitions of the test interface state machine TDI is the Test Data Input line, which supplies the data to the JTAG registers (BSR, Instruction Register etc.) TDI is the Test Data Input line, which supplies the data to the JTAG registers (BSR, Instruction Register etc.) TDO is the Test Data Output line, which is used to serially output the data from the JTAG registers to the equipment controlling the test TDO is the Test Data Output line, which is used to serially output the data from the JTAG registers to the equipment controlling the test Appendix B

54 JTAG registers Instruction Register (IR) – contains instruction which specifies the type of test to be performed, and the Data Register to be used during the test Instruction Register (IR) – contains instruction which specifies the type of test to be performed, and the Data Register to be used during the test Data Registers: Data Registers: The Device ID register (IDR) – reads out an identification number which is hardwired into the chip The Device ID register (IDR) – reads out an identification number which is hardwired into the chip The Bypass register (BR) – is a 1-cell pass-through register which connects the TDI to the TDO with 1-clock delay to give test equipment easy access to another device in the test chain on the same board The Bypass register (BR) – is a 1-cell pass-through register which connects the TDI to the TDO with 1-clock delay to give test equipment easy access to another device in the test chain on the same board The Boundary Scan register (BSR) – has already been described, intercepts all the signals between the core logic and the pins The Boundary Scan register (BSR) – has already been described, intercepts all the signals between the core logic and the pins In modern chips not only pins but also internal registers and memory cells can be included in the BSR (for example, FPGA configuration memory) In modern chips not only pins but also internal registers and memory cells can be included in the BSR (for example, FPGA configuration memory) Appendix B

55 How does it work? Test logic reset Run test idle Select IR chain Capture IR Shift IR Update IR Select DR chain Capture DR Shift DR Update DR N times IR or DR chain is selected by TMS input IR or DR chain is selected by TMS input Data Register is selected by contents of IR register Data Register is selected by contents of IR register Appendix B

56 Multi device debug Number of devices on the same board can be connected to single test chain Number of devices on the same board can be connected to single test chain 1 st device2 nd device TDI TRST TCK TMS TDO TDI=TDI 1 TDO 1 =TDI 2 TDO 2 =TDO JTAG port Appendix B

57 Debug tools for Virtex II Pro

58 Debug support The GNU Debugger (GDB) runs on the host machine and interfaces to the Xilinx Microprocessor Debugger (XMD) via TCP The GNU Debugger (GDB) runs on the host machine and interfaces to the Xilinx Microprocessor Debugger (XMD) via TCP XMD runs on the host machine and interfaces to the PowerPC target via JTAG interface XMD runs on the host machine and interfaces to the PowerPC target via JTAG interface ChipScope Pro software runs on the host machine and interfaces to the FPGA (not necessarily to PowerPC) via JTAG interface) ChipScope Pro software runs on the host machine and interfaces to the FPGA (not necessarily to PowerPC) via JTAG interface) Vision Probe hardware debugger interfaces to the PowerPC target via on-board debug port (JTAG compatible) and to the host machine software debugger SingleStep via parallel port Vision Probe hardware debugger interfaces to the PowerPC target via on-board debug port (JTAG compatible) and to the host machine software debugger SingleStep via parallel port GDB XMD Vision Probe PowerPC Virtex II Pro Target board Chip Scope Pro JTAG TCP Single Step Parallel

59 HW design for debug session Both Virtex II Pro and PowerPC have its own JTAG connection Both Virtex II Pro and PowerPC have its own JTAG connection The system must contain a JTAG_CNTL peripheral for debugging PowerPC through FPGA JTAG pins The system must contain a JTAG_CNTL peripheral for debugging PowerPC through FPGA JTAG pins PPC JTAG port may alternatively be routed to FPGA user I/O PPC JTAG port may alternatively be routed to FPGA user I/O MicroBlaze will always be debugged via FPGA JTAG port MicroBlaze will always be debugged via FPGA JTAG port FPGA JTAG or FPGA I/O This peripheral connects PowerPC JTAG pins to FPGA JTAG port and also connects correctly DEBUGHALT PowerPC port which is needed to stop processor from fetching and executing instructions

60 Using debuggers The Vision Probe hardware + SingleStep software debuggers are typically used for debugging of large amounts of software, such as RTOS, so we will find a little use in them The Vision Probe hardware + SingleStep software debuggers are typically used for debugging of large amounts of software, such as RTOS, so we will find a little use in them The GDB debugger still has many bugs, it is more preferably not to use it The GDB debugger still has many bugs, it is more preferably not to use it We will mostly use XMD and ChipScope Pro We will mostly use XMD and ChipScope Pro XMD is the command line, Unix-like debugger, preferable for software debug XMD is the command line, Unix-like debugger, preferable for software debug ChipScope Pro is scope-like tool, which gives a possibility to analyze external or internal signals of the design in run-time ChipScope Pro is scope-like tool, which gives a possibility to analyze external or internal signals of the design in run-time

61 XMD debugger

62 All PowerPC related commands start with “ x ” All PowerPC related commands start with “ x ” Useful XMD commands: Useful XMD commands: ppcconnect – establish connection between debugger and PowerPC target ppcconnect – establish connection between debugger and PowerPC target xdownload – download elf file to the target (we will use this command to download code to external memory) xdownload – download elf file to the target (we will use this command to download code to external memory) xreset – perform reset to the target xreset – perform reset to the target xcontinue – run target from certain address xcontinue – run target from certain address xrreg / xwreg – read / write PowerPC registers xrreg / xwreg – read / write PowerPC registers xrmem / xwmem – read / write memory xrmem / xwmem – read / write memory and many other … and many other … There are similar MicroBlaze commands without “ x ” There are similar MicroBlaze commands without “ x ” For connect to MicroBlaze target we will use “ mbconnect ” For connect to MicroBlaze target we will use “ mbconnect ”

63 ChipScope Pro

64 ChipScope Pro consists of 3 different programs: ChipScope Pro consists of 3 different programs: ChipScope Core generator ChipScope Core generator Creates configurable cores of Integrated Bus Analyzer (IBA) Creates configurable cores of Integrated Bus Analyzer (IBA) ChipScope Core inserter ChipScope Core inserter Inserts created core to the design Inserts created core to the design ChipScope Analizer ChipScope Analizer Establishes connection to IBA core inside the design and presents signals activity Establishes connection to IBA core inside the design and presents signals activity IBA is a core that can be connected to any signal existing in the design IBA is a core that can be connected to any signal existing in the design IBA samples connected signals when trigger condition occurs IBA samples connected signals when trigger condition occurs Number of samples, trigger signals and conditions are simply configured Number of samples, trigger signals and conditions are simply configured Sampled data is saved to BRAMs and later presented to the user Sampled data is saved to BRAMs and later presented to the user ChipScope Pro can be used in any design, regardless of existing PowerPC core in the design ChipScope Pro can be used in any design, regardless of existing PowerPC core in the design

65 ChipScope Pro system block diagram Integrated CONtroller Integrated Logic Analyzer (up to 15)

66 Chip Scope Pro design flow Simpler and preferred

67 Chip Scope Pro design flow Synthesize design using EDK or external tool Create ILA and insert it to design using Chip Scope Pro Inserter project.edf or project.ngc ILA definitions project.ngo P&R new design with Project Navigator project.bit Return to EDK to update bitstream with software Update bitstream with software from iMPACT (download tool) Download bitsream to the board Run Chip Scope Pro Analyzer to analyze design Start with HDL source files and system description (MHS, MPD)

68 Chip Scope Pro design flow Your netlist Generated netlist Target device SRL-Set Reset Latch RPM – Relationally placed macro

69 Chip Scope Pro design flow Use it only if you don ’ t have enough global buffers for your logic (introduces skew)

70 Chip Scope Pro design flow Up to 16 trigger ports Trigger width up to 256 A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port. The results of one or more match units are combined together to form the overall trigger condition event that is used to control the capturing of data Up to 16 match units for each trigger and overall Trigger Sequencer allows building state machine based on all match units so that trigger condition will satisfied after machine passes all its states

71 Chip Scope Pro design flow Check that total number of BRAMs used by Chip Scope and by you doesn ’ t exceed number of BRAMs in FPGA Check it, if you want to sample triggers only

72 Chip Scope Pro design flow Double click on one of them to connect signals

73 Chip Scope Pro design flow Design nets Press here to connect signals

74 Chip Scope Pro design flow When all signals are connected, core insertion is performed When all signals are connected, core insertion is performed New netlist is created New netlist is created Bitstream generation can be performed in Project Navigator Bitstream generation can be performed in Project Navigator

75 Finishing Chip Scope Pro design flow Open Project Navigator, create new project:

76 Finishing Chip Scope Pro design flow Important: Don ’ t select them! File created by Chip Scope Pro inserter … Add files …

77 Finishing Chip Scope Pro design flow BMM file is required for generating memory Double click to generate bitstream

78 Finishing Chip Scope Pro design flow When starting, IMPACT will display wizard which will guide you through the programming process When starting, IMPACT will display wizard which will guide you through the programming process Attention: download cable should be connected and board power on before running IMPACT ! If there are no problems with JTAG, 3 devices are recognized on the board: First two devices are on-board PROMS, we are not interested in them (press Cancel twice) Virtex II PRO is the third in the JTAG chain of the board

79 Finishing Chip Scope Pro design flow Right click on Virtex II PRO and select “ Assign new configuration file ” Right click on Virtex II PRO and select “ Assign new configuration file ” Select required “.bit” file and press “Open” Right click on Virtex II PRO and select “Program” Press “OK” – device will start programming: Add here updated “.bmm” and “.elf” files

80 Using Chip Scope Pro Analyzer Invocation:

81 Invocation: Open analyzer after downloading bitstream to the board Open analyzer after downloading bitstream to the board Close iMPACT before accessing JTAG from analyzer ! Close iMPACT before accessing JTAG from analyzer ! Press here to connect to JTAG chain Press here to connect to JTAG chain

82 Using Chip Scope Pro Analyzer Analyzer main window after connecting to JTAG Analyzer main window after connecting to JTAG Signals list (here names of signals can be changed) Waveform window (two markers) Messages & Warnings Debug configuration Trigger settings

83 Using Chip Scope Pro Analyzer Define here function (==, <>, ) of match unit and its value Define here trigger condition Very limited possibilities: All match units can be either ANDed or ORed, with additional possibility of NOT on whole expression

84 Using Chip Scope Pro Analyzer Using level sequencer: Using level sequencer:

85 Using Chip Scope Pro Analyzer Capture setting tab: Capture setting tab: There are two modes of capturing: There are two modes of capturing: Window Window N Samples N Samples In window mode, once trigger condition satisfied, data is sampled for defined number of cycles (512, 1024 etc.) In window mode, once trigger condition satisfied, data is sampled for defined number of cycles (512, 1024 etc.) In N samples mode, each time trigger condition is satisfied, data is sampled for N cycles In N samples mode, each time trigger condition is satisfied, data is sampled for N cycles Total number of samples, however, cannot exceed defined previously depth Total number of samples, however, cannot exceed defined previously depth

86 Using Chip Scope Pro Analyzer Signals can be bundled to bus to simplify waveform view: Signals can be bundled to bus to simplify waveform view: Start capturing: Start capturing: Capture from now according to trigger condition Stop capturing Unconditional capture

87 Summary - demonstration System including next components will be demonstrated: System including next components will be demonstrated: PPC405 processor PPC405 processor 32K of PLB BRAM 32K of PLB BRAM PLB2OPB bridge PLB2OPB bridge 16K of OPB BRAM 16K of OPB BRAM 32M of OPB SDRAM 32M of OPB SDRAM OPB GPIO for interface with leds, switches, push buttons and lcd OPB GPIO for interface with leds, switches, push buttons and lcd OPB UART for interface with computer OPB UART for interface with computer Simple program runs on PPPC405 Simple program runs on PPPC405

88 System block diagram PPC405 PLB bus BRAM BRAM controller JTAG interface BUS arbiter PLB to OPB bridge BUS arbiter OPB bus BRAM BRAM controller GPIO DIP switches Push buttons GPIO LCDLEDs UART Hyper Terminal SDRAM controller SDRAM Off-chip FPGA JTAG port Reset block RST

89 System build flow Hardware flow – platform build Add required cores to the design -> peripherals -> peripherals Add required cores to the design -> peripherals -> peripherals Define address space for BRAM, SDRAM, GPIOs, UART, OPB -> peripherals -> peripherals Define address space for BRAM, SDRAM, GPIOs, UART, OPB -> peripherals -> peripherals Connect PPC and one of BRAMs to PLB, all the other cores to OPB -> bus conn. -> bus conn. Connect PPC and one of BRAMs to PLB, all the other cores to OPB -> bus conn. -> bus conn. Choose port A BRAM connection for both BRAMs -> bus conn. -> bus conn. Choose port A BRAM connection for both BRAMs -> bus conn. -> bus conn. Define external ports (UART rx, tx, SDRAM address and data etc.) Connect internal ports by signals (connect clock to all cores, connect JTAG block to PPC etc.) -> ports -> ports Define external ports (UART rx, tx, SDRAM address and data etc.) Connect internal ports by signals (connect clock to all cores, connect JTAG block to PPC etc.) -> ports -> ports Define generics for cores where it is required (for example, UART baud rate) -> parameters -> parameters Define generics for cores where it is required (for example, UART baud rate) -> parameters -> parameters

90 System build flow Hardware flow – platform generation Define platform (previous slide) Choose XPS design flow (Project Options window) Generate netlist Define pins in ucf file Generate bitstream (system.bit file) Generate bitstream (system.bit file)

91 System build flow Write simple C program Define level 1 drivers for GPIO and level 0 for other cores Define UART as standard I/O peripheral for PPC Define operating system as standalone, core freq. 100 Mhz. and location for output elf file Generate libraries For running from BRAM, define program start address 0xFFFF8000 (BRAM resides at this address) For running from SDRAM, define program start address 0x0 (SDRAM resides at this address) Compile program Software flow

92 System build flow For running from BRAM Run Data2BRAM download.bit file is created Run Data2BRAM download.bit file is created Download to FPGA from EDK Download via iMPACT download.bit file Download via iMPACT download.bit file For running from SDRAM Download via iMPACT system.bit file Download via iMPACT system.bit file Run XMD Download via XMD executable.elf file Download via XMD executable.elf file Implementation

93

94 Essential links EDK Tutorials EDK Tutorials Virtex II Pro architecture (FPGA, BRAM, DCM, Multipliers) Virtex II Pro architecture (FPGA, BRAM, DCM, Multipliers) PPC405 block architecture (OCM, processor I/O interfaces) PPC405 block architecture (OCM, processor I/O interfaces) PowerPC processor architecture (inside) PowerPC processor architecture (inside) PLB, OPB and other cores PLB, OPB and other cores Information can be found by opening PDFs from the EDK Information can be found by opening PDFs from the EDK EDK, XMD, drivers, adding user cores, MicroBlaze processor EDK, XMD, drivers, adding user cores, MicroBlaze processor ChipScope Pro ChipScope Pro In addition, all the information is on the Q:\Virtex II Pro In addition, all the information is on the Q:\Virtex II Pro

95 MicroBlaze based SoPC architectire Appendix A

96 MicroBlaze buses Local Memory bus (LMB) Local Memory bus (LMB) 32-bit high speed memory access 32-bit high speed memory access Single-cycle to on-chip BRAM Single-cycle to on-chip BRAM ILMB (Instruction LMB) ILMB (Instruction LMB) DLMB (Data LMB) DLMB (Data LMB) On-Chip Peripheral bus (OPB) On-Chip Peripheral bus (OPB) 32-bit processor interface 32-bit processor interface 8/16/32-bit peripheral interface 8/16/32-bit peripheral interface IOPB (instruction OPB) IOPB (instruction OPB) DOPB (data OPB) DOPB (data OPB) Appendix A


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