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Virtex II Pro based SoPC design Part 1 Introduction.

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1 Virtex II Pro based SoPC design Part 1 Introduction

2 Before we start … The guidance consists of two parts: The guidance consists of two parts: Introduction Introduction SoPC concept SoPC concept Working platforms Working platforms Design Flow – building basic system Design Flow – building basic system Advanced topics Advanced topics Adding user cores Adding user cores Debug (ChipScope) Debug (ChipScope) JTAG JTAG Simulation Simulation Today

3 Outline SoPC design concept SoPC design concept SoPC platform SoPC platform Memec design board Memec design board ML310 design board ML310 design board Virtex II Pro Architecture Virtex II Pro Architecture PPC architecture PPC architecture Processor Buses Processor Buses SoPC implementation flow SoPC implementation flow

4 Part 1 Introduction and SoPC platform

5 System evolution Old systemsRecent systemsModern systems Time System complexity and density Components of the system are large. “In-room” interconnect All components reside in relatively small box. On-board interconnect Components of the system reside on single chip. On-chip interconnect We are here

6 SoC glossary IP (Intellectual Property) – In integrated circuits, predefined large functions, called “ cores ”, that help the user complete a large design faster IP (Intellectual Property) – In integrated circuits, predefined large functions, called “ cores ”, that help the user complete a large design faster Soft IP (soft core) – A synthesizable IP which can be readily incorporated into an FPGA Soft IP (soft core) – A synthesizable IP which can be readily incorporated into an FPGA Hard IP (hard core) – An IP which placed on FPGA during fabrication process and resides there all the time Hard IP (hard core) – An IP which placed on FPGA during fabrication process and resides there all the time

7 SoC design process Choose chip with required hard cores inside Add required soft cores Add user logic

8 SoC platform System on Chip System On Chip Application Specific Integrated Circuit System On Programmable Chip Field Programmable Gate Array We are here

9 SoPC platform - inside Virtex II Pro FPGA (XC2VP7) Virtex II Pro FPGA (XC2VP7) ~1M ASIC gates ~1M ASIC gates 44 18x18-bit Multipliers 44 18x18-bit Multipliers 88 KB of on-chip memory 88 KB of on-chip memory Power PC 4.05 CPU core Power PC 4.05 CPU core 4 2.5Gbps Rocket I/O transceivers 4 2.5Gbps Rocket I/O transceivers 4 DCM (digital clock manager) units 4 DCM (digital clock manager) units There are more power configurations There are more power configurations

10 SoPC platform - outside Virtex II Pro FPGA resides on Memec Development board, including: Virtex II Pro FPGA resides on Memec Development board, including: 32 MB of SDRAM 32 MB of SDRAM 100MHz & 125 MHz clocks 100MHz & 125 MHz clocks 2x16 LCD panel 2x16 LCD panel 8 user DIP switches 8 user DIP switches 4 user leds 4 user leds 4 user push buttons 4 user push buttons Serial port interface Serial port interface JTAG port JTAG port Hardware debugger port Hardware debugger port Extension to P160 card Extension to P160 card

11 SoPC platform - outside P160 communication card includes, in addition to resources available on board: P160 communication card includes, in addition to resources available on board: 8M of Flash memory 8M of Flash memory 1M of SRAM memory 1M of SRAM memory Ethernet 10/100 port Ethernet 10/100 port USB port USB port Additional serial port Additional serial port PS / 2 port PS / 2 port External LCD interface External LCD interface

12 ML310 development board

13 Virtex II Pro architecture overview

14 Configurable logic block (CLB) Input Output Block (IOB)

15 Virtex II Pro architecture overview Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM

16 Virtex II Pro architecture overview Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier

17 Virtex II Pro architecture overview Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver

18 Virtex II Pro architecture overview Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver Digital Clock Manager (DCM)

19 Virtex II Pro architecture overview Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver Digital Clock Manager (DCM) Power PC CPU core

20 Virtex II Pro architecture overview Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver Digital Clock Manager (DCM) Processor block Global and local routing

21 Block SelectRAM+ (BRAM) 44 blocks of 18 Kb each True dual-port RAM Fully synchronous Parity bits can be used Possible configurations: 16K x 1 bit 2K x 9 bits 8K x 2 bits 1K x 18 bits 4K x 4 bits 512 x 36 bits DIA DIPA ADDRA WEA WNA SSRA DOA CLKA DOPA DIB DIPB ADDRB WEB ENB SSRB DOB CLKB DOPB

22 Processor block overview CPU-FPGA interfaces 405 Core Control Logic OCM controller OCM Controller BRAM FPGA CLB Array Interface Logic Processor Block = CPU core + Interface Logic + CPU-FPGA interface

23 On-chip Memory (OCM) Controller OCM controller is designed to provide very quick access to a fixed amount of instruction and data memory space OCM controller is of a distributed style and it is split into 2 blocks Instruction Side OCM (ISOCM) Data side OCM (DSOCM) Instruction Side OCM: 64-bit read only bus (two instructions per cycle) Can support 128 KB of BRAM (if available on FPGA) Writing to ISBRAM during BRAM initialization only Data Side OCM: 32-bit data read and 32-bit data write buses Can support 64 KB of BRAM (if available on FPGA) Writing to DSBRAM during BRAM init, by CPU, FPGA via second port OCM is not cacheable memory !

24 On-chip Memory (OCM) Controller 405 Core Data Side BRAM: Transient data storage Bi-directional data transfer – – Packet Processing D Side Controller BRAM Soft IP in Fabric Instruction Side BRAM: Boot code Interrupt Service Routines – – Deterministic low latency I Side Controller BRAM Fixed Logic

25 PPC 405 Core organization 5-stage pipeline 5-stage pipeline Fetch Fetch Decode Decode Execute Execute Write-back Write-back Load write-back Load write-back Memory Management Unit Memory Management Unit Separate Instruction and Data cache units Separate Instruction and Data cache units Debug support, including a JTAG interface Debug support, including a JTAG interface Three programmable timers Three programmable timers

26 PPC 405 Core parts - CPU 5-stage pipeline 5-stage pipeline 3-element fetch queue : 2 prefetch buffers + decode buffer 3-element fetch queue : 2 prefetch buffers + decode buffer Static branch prediction Static branch prediction Execution unit consist of GPR, MAC and ALU Execution unit consist of GPR, MAC and ALU bit registers with 3 read and 2 write ports bit registers with 3 read and 2 write ports Floating point operations are not supported! Floating point operations are not supported! Single-cycle throughput in MAC instructions Single-cycle throughput in MAC instructions

27 PPC 405 Core parts - Interrupts Critical and non critical interrupts are supported Critical and non critical interrupts are supported Caused by: Caused by: Error conditions Error conditions Internal timers Internal timers Debug events Debug events External interrupt controller (EIC) interface External interrupt controller (EIC) interface 2 EIC interrupts are supported 2 EIC interrupts are supported

28 PPC 405 Core parts - MMU 4 GB of flat address space 4 GB of flat address space Multiple page sizes supported Multiple page sizes supported 1KB to 16MB pages (8 types) 1KB to 16MB pages (8 types) Software controlled Software controlled 64 entries fully associative TLB 64 entries fully associative TLB Software controlled Software controlled Storage attributes are provided to control access of memory regions Storage attributes are provided to control access of memory regions

29 PPC 405 Core parts - Caches Independent instruction and data caches Independent instruction and data caches 16-KB, 2-way set associative, 32 byte line 16-KB, 2-way set associative, 32 byte line Non-blocking caches Non-blocking caches LRU replacement policy LRU replacement policy Write through / write back DCU Write through / write back DCU Both have PLB master interface Both have PLB master interface

30 PPC 405 Core parts – Debug Four debug modes Four debug modes Internal-debug : software debuggers Internal-debug : software debuggers External-debug : JTAG debuggers External-debug : JTAG debuggers Debug-wait : interrupt servicing during processor appears to be stopped Debug-wait : interrupt servicing during processor appears to be stopped Real-time trace : instruction trace tools Real-time trace : instruction trace tools JTAG debug interface JTAG debug interface

31 SoPC architecture Our SoPC based on CoreConnect standart Our SoPC based on CoreConnect standart

32 CoreConnect bus architecture Processor Local Bus (PLB) 32-bit address, 64-bit data Separate read and write buses High performance Low load On-Chip peripheral bus (OPB) 32-bit address, 32-bit data Max peripherals High load Device Control Register bus (DCR) 32-bit transfer to and from GPR Direct accessible by PPC

33 The PLB and OPB buses The PLB can be thought of as the “ Motorway ” of the CoreConnect bus structure The PLB can be thought of as the “ Motorway ” of the CoreConnect bus structure The PLB is fast and has a very high bandwidth The PLB is fast and has a very high bandwidth There is a direct connection to the processor from the PLB There is a direct connection to the processor from the PLB The OPB can be thought of as the “ A Road ” of CoreConnect The OPB can be thought of as the “ A Road ” of CoreConnect The OPB is a lower bandwidth bus designed to accommodate the needs of slower peripherals (UARTS, GPIO, etc.) The OPB is a lower bandwidth bus designed to accommodate the needs of slower peripherals (UARTS, GPIO, etc.) Use of the OPB allows the PLB to remain free of the slower traffic and thus work more effectively Use of the OPB allows the PLB to remain free of the slower traffic and thus work more effectively There is no connection to PPC from the OPB There is no connection to PPC from the OPB The two buses are connected by an “ OPB Bridge ” – just like a motorway junction The two buses are connected by an “ OPB Bridge ” – just like a motorway junction

34 The DCR bus The DCR bus in not used to carry any sort of data which can be processed by the execution units, nor does it carry instructions The DCR bus in not used to carry any sort of data which can be processed by the execution units, nor does it carry instructions DCRs (the registers themselves, not the bus) can be thought of as “ flags ”. These flags can be set to define the operating mode for processor peripherals. DCRs (the registers themselves, not the bus) can be thought of as “ flags ”. These flags can be set to define the operating mode for processor peripherals. E.g. criticality of interrupts, DMA channel control, UART communication modes etc. E.g. criticality of interrupts, DMA channel control, UART communication modes etc. DCR registers exist outside of the core, so the DCR bus is used to communicate with with registers DCR registers exist outside of the core, so the DCR bus is used to communicate with with registers

35 Processor block interfaces The processor block provides I/O signals grouped functionally into the following interfaces: The processor block provides I/O signals grouped functionally into the following interfaces: PLB interface PLB interface 32-bit address and three 64-bit data buses 32-bit address and three 64-bit data buses DCR interface DCR interface Attachment of on-chip registers for device control Attachment of on-chip registers for device control Clock and Power Management (CPM) Clock and Power Management (CPM) JTAG port JTAG port Debugging Debugging On-chip interrupt controller On-chip interrupt controller Critical and non-critical interrupts Critical and non-critical interrupts On-chip memory controller On-chip memory controller Reset interface Reset interface Three types of reset Three types of reset

36 Part 2 SoPC design using XILINX Tools

37 Hardware / Software flow How is Embedded system created? How is Embedded system created? Hardware design flow Hardware design flow Software design flow Software design flow Integration Integration Embedded development Kit (EDK) Embedded development Kit (EDK) Assists in creating system hardware definition Assists in creating system hardware definition Calls XILINX ISE for FPGA implementation Calls XILINX ISE for FPGA implementation Assists in creation of software code Assists in creation of software code GNU Cross Compiler / Debugger (GCC / GDB) GNU Cross Compiler / Debugger (GCC / GDB) XILINX Microprocessor Debugger (XMD) XILINX Microprocessor Debugger (XMD)

38 SoPC Design Tool Chain C/C++ code Compiler / Linker Object code Download to FPGA PPC code in off- chip memory VHDL / Verilog Simulator Synthesizer Place & Route Download to FPGA Data2BRAM.elf.bit Debugger Chip Scope Pro Tools Standard Software Flow Standard Hardware Flow PPC code in on- chip memory

39 EDK ISE Where does EDK assist? HW Block diagram SW flow chart HW description Create SW source Bit file / download Elf file / download Synthesize, P&R Compile Design Debug (HW and SW) DATA2BRAM Hardware Flow Software Flow

40 Using BSB to create new project Base System Builder is wizard helping you build system in easy way

41 Using BSB to create new project

42

43

44 Creating project without BSB

45 Project directory structure Additional directories are created after synthesis Projects directory name Current project name Must be without spaces code This directory will typically contain user c and h files data Here ucf (user constraint file) resides pcores User defined cores should be placed here sim Files needed for simulation ppc405code include lib Here will be compiled and linked code (elf) Files generated during software flow drivers Drivers for user defined cores should be placed here

46 EDK main window System description System block diagram Message window

47 System description System cores Main files

48 EDK- Hardware flow Specify processor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA

49 Specify cores Choose core version Address space must be specified if needed

50 Specify buses Specifying master / slave interface on the bus(es) Specifying BRAM port

51 Connecting components

52 Changing cores generics

53 Hardware flow - MHS Microprocessor Microprocessor Hardware Specification file A text file that describes the hardware structure A text file that describes the hardware structure Processor Processor Bus architecture Bus architecture Peripherals Peripherals Connectivity of the system Connectivity of the system Address space Address space Specify processor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA

54 Hardware flow - MPD Microprocessor Microprocessor Peripheral Definition file Template that specifies ports and parameters of IP Template that specifies ports and parameters of IP List ports and default connectivity for bus interfaces List ports and default connectivity for bus interfaces List parameters and default values List parameters and default values Any MPD parameter is overwritten by equivalent MHS assignment Any MPD parameter is overwritten by equivalent MHS assignment Specify processor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA

55 Hardware flow – Platform generator Platform Generator (Platgen) Platform Generator (Platgen) Uses MHS and MPD files to create hardware platform Uses MHS and MPD files to create hardware platform Creates HDL wrappers Creates HDL wrappers Creates netlist files (EDF, NGC) Creates netlist files (EDF, NGC) Creates support files for downstream tools Creates support files for downstream tools Specify professor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA

56 Hardware flow – Implementation Implementation flow Implementation flow XFlow XFlow Batch mode place & route flow Batch mode place & route flow ProjNav ProjNav ISE Project Navigator place & route flow ISE Project Navigator place & route flow Specify professor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA

57 EDK – software flow After peripheral hardware definition, the software is independent on the hardware flow Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Download to FPGA Data2BRAM Bitsream Hardware flow Execute in off-chip memory Execute in on-chip memory GDB / XMD

58 Software flow - MSS Microprocessor Software Specification Auto-generated / user modifiable Contain all project software options Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Download to FPGA Data2BRAM Bitsream Hardware flow Execute in off-chip memory Execute in on-chip memory GDB / XMD

59 Software flow - MDD Microprocessor Driver Definition Describes configurable parameters in a driver Defines driver dependencies Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable

60 Software platform settings Double click on any peripheral to open software settings window OS : standalone, VxWorks, Linux, xilkernel

61 Software platform settings (2) Frequency: used for different time-related functions Should be set to actual h/w frequency (100 Mhz)

62 Software platform settings (3) Definition of standard I/O, i.e. printf and scanf will be mapped to these devices

63 Software applications Memory parameters of the application (default start address is 0x0, default heap + stack size is 400 bytes) Software code to be downloaded to memory

64 Adding source files

65 Software flow – Code compilation Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable After software compilation ELF file is created After software compilation ELF file is created Executable and Executable and Linking Linking Format Format

66 When software meets hardware … The contents of.bit file (hardware) can be updated with contents of.elf file (software) The contents of.bit file (hardware) can be updated with contents of.elf file (software) downloadable.bit file DATA2BRAM.elf file (software).bit file (hardware).bit file describes hardware platform, BRAM contents undefined.bmm file.bmm file maps defined BRAM memory to actual BRAM blocks here.bit file describes hardware platform with BRAM contents updated with program code BRAM BRAM Memory Memory Map Map

67 Software flow – Library generator Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Directory Structure after executing the Libgen Command: Directory Structure after executing the Libgen Command: code folder will contain the user output program file (executable.elf) code folder will contain the user output program file (executable.elf) include folder contains header files for this design include folder contains header files for this design libsrc folder contains source files for the drivers used in this design libsrc folder contains source files for the drivers used in this design lib folder contains standart C, Math and Xilinx libraries lib folder contains standart C, Math and Xilinx libraries

68 Downloading to the board Downloading the bitstream to hardware can be accomplished one of to ways: Downloading the bitstream to hardware can be accomplished one of to ways: With the EDK With the EDK With the ISE iMPACT With the ISE iMPACT

69 Tools invocation Libraries generation Code compilation Netlist generation Bitsream generation Data to BRAM Downloading bitsream After software changes, Data2BRAM can be performed without re-generating of bitsream After software changes, Data2BRAM can be performed without re-generating of bitsream To run all the flow enough to invoke “ Data2BRAM ” or “ Downloading bitsream ” To run all the flow enough to invoke “ Data2BRAM ” or “ Downloading bitsream ” When using ProjNav, “ bitsream generation ” icon is inaccessible When using ProjNav, “ bitsream generation ” icon is inaccessible

70 Essential links EDK Tutorials EDK Tutorials Virtex II Pro architecture (FPGA, BRAM, DCM, Multipliers) Virtex II Pro architecture (FPGA, BRAM, DCM, Multipliers) PPC405 block architecture (OCM, processor I/O interfaces) PPC405 block architecture (OCM, processor I/O interfaces) PowerPC processor architecture (inside) PowerPC processor architecture (inside) PLB, OPB and other cores PLB, OPB and other cores Information can be found by opening PDFs from the EDK Information can be found by opening PDFs from the EDK EDK, drivers, adding user cores, MicroBlaze processor EDK, drivers, adding user cores, MicroBlaze processor In addition, all the information is on the Q:\Virtex II Pro In addition, all the information is on the Q:\Virtex II Pro

71 Summary - demonstration System including next components will be demonstrated: System including next components will be demonstrated: PPC405 processor PPC405 processor 32K of PLB BRAM 32K of PLB BRAM PLB2OPB bridge PLB2OPB bridge 16K of OPB BRAM 16K of OPB BRAM 32M of OPB SDRAM 32M of OPB SDRAM OPB GPIO for interface with leds, switches, push buttons and lcd OPB GPIO for interface with leds, switches, push buttons and lcd OPB UART for interface with computer OPB UART for interface with computer Simple program runs on PPPC405 Simple program runs on PPPC405

72 System block diagram PPC405 PLB bus BRAM BRAM controller JTAG interface BUS arbiter PLB to OPB bridge BUS arbiter OPB bus BRAM BRAM controller GPIO DIP switches Push buttons GPIO LCDLEDs UART Hyper Terminal SDRAM controller SDRAM Off-chip FPGA JTAG port Reset block RST

73 System build flow Hardware flow – platform build Add required cores to the design -> peripherals -> peripherals Add required cores to the design -> peripherals -> peripherals Define address space for BRAM, SDRAM, GPIOs, UART, OPB -> peripherals -> peripherals Define address space for BRAM, SDRAM, GPIOs, UART, OPB -> peripherals -> peripherals Connect PPC and one of BRAMs to PLB, all the other cores to OPB -> bus conn. -> bus conn. Connect PPC and one of BRAMs to PLB, all the other cores to OPB -> bus conn. -> bus conn. Choose port A BRAM connection for both BRAMs -> bus conn. -> bus conn. Choose port A BRAM connection for both BRAMs -> bus conn. -> bus conn. Define external ports (UART rx, tx, SDRAM address and data etc.) Connect internal ports by signals (connect clock to all cores, connect JTAG block to PPC etc.) -> ports -> ports Define external ports (UART rx, tx, SDRAM address and data etc.) Connect internal ports by signals (connect clock to all cores, connect JTAG block to PPC etc.) -> ports -> ports Define generics for cores where it is required (for example, UART baud rate) -> parameters -> parameters Define generics for cores where it is required (for example, UART baud rate) -> parameters -> parameters

74 System build flow Hardware flow – platform generation Define platform (previous slide) Choose XPS design flow (Project Options window) Generate netlist Define pins in ucf file Generate bitstream (system.bit file) Generate bitstream (system.bit file)

75 System build flow Write simple C program Define level 1 drivers for GPIO and level 0 for other cores Define UART as standard I/O peripheral for PPC Define operating system as standalone, core freq. 100 Mhz. and location for output elf file Generate libraries For running from BRAM, define program start address 0xFFFF8000 (BRAM resides at this address) For running from SDRAM, define program start address 0x0 (SDRAM resides at this address) Compile program Software flow

76 System build flow For running from BRAM Run Data2BRAM download.bit file is created Run Data2BRAM download.bit file is created Download to FPGA from EDK Download via iMPACT download.bit file Download via iMPACT download.bit file For running from SDRAM Download via iMPACT system.bit file Download via iMPACT system.bit file Run XMD Download via XMD executable.elf file Download via XMD executable.elf file Implementation

77 MicroBlaze based SoPC architectire Appendix A

78 MicroBlaze buses Local Memory bus (LMB) Local Memory bus (LMB) 32-bit high speed memory access 32-bit high speed memory access Single-cycle to on-chip BRAM Single-cycle to on-chip BRAM ILMB (Instruction LMB) ILMB (Instruction LMB) DLMB (Data LMB) DLMB (Data LMB) On-Chip Peripheral bus (OPB) On-Chip Peripheral bus (OPB) 32-bit processor interface 32-bit processor interface 8/16/32-bit peripheral interface 8/16/32-bit peripheral interface IOPB (instruction OPB) IOPB (instruction OPB) DOPB (data OPB) DOPB (data OPB) Appendix A


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