1. ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
Canon Four Levels per Mask Plate
Stepper Jobs
Dr. Lynn Fuller
Webpage:
Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY
Tel (585)
Fax (585)
Department webpage:
Canon_4X1_Masks.ppt

2. OUTLINE
Introduction
Chip Design
Calculations
Mask Example
Approach
Level 1 Details
Level 2,3,4,5,6,7,8,9,10,11,12 Details
Results

3. INTRODUCTION
Placing four photo levels on one mask plate can reduce the number of mask plates by a factor of four. This saves time, costs and inventory of masks needed for projects. For example a 12 level mask set for CMOS will require only 3 mask plates.
The disadvantage of this approach is that the chip size is limited to 10mm by 10mm compared to 20mm by 20mm for 1 level per plate masks.
The stepper jobs are slightly more complicated but once created provide the same overlay and resolution.

4. CALCULATING SHIFTS TO OVER LAY LEVELS 2,3,4,5
The first layer is placed on the wafer with no alignment. Lets use an example where a chip has its TVPA marks in the center of the chip and the B scope multi-marks are slightly above, and C scope multi-marks are slightly to the left.
Center of shot is placed under the center of the optical column 1 2 4 3 1 2 4 3
Level 1 2 4 3 1 2 4 3 1 2 4 3
The Mask from non chrome side
Each level is centered +/- 20 mm from the center of the plate
Wafer after 1st exposure with blades wide open

5. CALCULATING SHIFTS TO OVER LAY LEVEL 2
The subsequent layers are aligned by locating the center of the TVPA and multi-marks from the first layer. Then calculating the center of the chip and moving it under the center of the optical column and make the shot. If in the stepper job the TVPA mark is given as X=0 and Y=0 the shot will be made with the 1st level TVPA under the center of the optical column resulting in exposure as shown. To get level 2 (red) to overlay level 1(green) we give x = -4mm and y = -4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer -4 mm in x and -4mm in y when moving the wafer under the center of the optical column. Thus placing the 3rd quadrant (level 2) over the 2nd quadrant (level 1) as desired. 1 2 4 3 1 2 4 3
Level 1 2 4 3
The Mask from non chrome side
Wafer after 1st exposure with blades wide open

6. CALCULATING SHIFTS TO OVER LAY LEVELS 3
To get level 3 to overlay level 1(green) we give x = -4mm and y = +4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer -4 mm in x and +4mm in y when moving the wafer under the center of the optical column. Thus placing the 4th quadrant (level 3) over the 2nd quadrant (level 1) as desired. 1 2 4 3 1 2 4 3
Level 1 2 4 3
The Mask from non chrome side
Wafer after 1st exposure with blades wide open

7. CALCULATING SHIFTS TO OVER LAY LEVEL 4
To get level 4 to overlay level 1(green) we give x = +4mm and y = +4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer +4 mm in x and +4mm in y when moving the wafer under the center of the optical column. Thus placing the 1 st quadrant (level 4) over the 2nd quadrant (level 1) as desired. 1 2 4 3 1 2 4 3
Level 1 2 4 3
The Mask from non chrome side
Wafer after 1st exposure with blades wide open

8. CALCULATING SHIFTS TO OVER LAY LEVEL 5
To get level 5 to overlay level 1(green) we give x = -4mm and y = +4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer -4 mm in x and +4mm in y when moving the wafer under the center of the optical column. Thus placing the 2 st quadrant (level 5) over the 2nd quadrant (level 1) as desired. 1 2 4 3 1 2 4 3
Level 5 6 8 7
The Mask from non chrome side
Wafer after 1st exposure with blades wide open

9. MIXED SUB-CMOS CHIP DESIGN
Alignment Keys
(Xur,Yur)
(X,Y)
(X,Y)
(X,Y)
(X,Y)
(X,Y)
(0,0)

10. SMALL CMOS MASK EXAMPLE 8mmX8mm
Level 1 nwell
Level- 1
Center at
-20,20
Level- 4
Center at
20,20
Level 4 PVt
Alignment Keys
Fiducial Mark
Fiducial Mark
0,0
Level 3 stop
Level 2 active
Level- 2
Center at
-20,-20
Level- 3
Center at
20,-20
Keys
View from Non-Chrome Side

11. LARGE CMOS MASK EXAMPLE 10mmX10mm
View from Non-Chrome Side
Level- 1
Center at
-25,25
Level- 4
Center at
25,25
Level 1 nwell
Level 4 Vt
Fiducial Mark
Fiducial Mark
Alignment Keys
0,0
Level 3 stop
Level 2 active

12. CALCULATIONS FOR MIXED SUB-CMOS

13. CALCULATIONS FOR PMOS (SHORTCOURSE)

14. CALCULATIONS FOR LARGE CMOS TEMPLATE

15. APPROACH
First Level Exposure – cover the 1st, 3rd and 4th quadrants of the mask using the blade position in the shot file.
- In the layout file create a block and shift the block CQ/5 mm in X and –CQ/5 mm in Y to center the array on the wafer.
- In the process file select 1st Level – no alignment
Second level Exposure – cover the 1st, 2nd and 4th quadrants of the mask using the blade position in the shot file.
-no shift in the layout file (Otherwise same as level 1)
- Shift the PA and Fine Alignment Mark positions on page 4 and 13 of the process file
Third level Exposure – cover the 1st, 2nd and 3rd quadrants of the mask using the blade position in the shot file.
-no shift in the layout file

16. BLADE POSITIONS FOR SHOT FILES
LEVEL 1
2nd Quadrant
LEVEL 2
3nd Quadrant
LEVEL 3
4nd Quadrant
LEVEL 4
1st Quadrant BL
-10mm BR
10mm BU BD
Level 1
Bu = +10 mm
Br = 0 mm
Bl = -10 mm
(0,0)
Bd = 0 mm
Blade positions are in mm referenced at the wafer.

17. 1st LEVEL LAYOUT FILE #### LAYOUT EDITOR (File ID)### (page-1)
File name;
1. Comment;
#### LAYOUT EDITOR (File ID)### (page-2)
1. Matrix Invalid Area:
2. Step Size; Sx = Sy =
3. Matrix; Clm = Row =
4. Origin; X= Y=
5. Reticle Table Name ;
Lmixed4X1_nwell
anything you want
13 mm
8.2 mm
8.2 mm 14 14
0 mm
0 mm
RF012subcmos
On page 2 you can create and shift blocks

18. 1ST LEVEL LAYOUT CREATE AND SHIFT BLOCK
Select Function Key “Modify”
Select Function Key “Other Menu”
Select Function Key “Shift Copy Block”
Select Function Key “Add Block”
Row *
Column * Go
Go Sure? 1 = Yes
Select Function Key “Shift Block”
X = 4mm
Y = -4mm
Clear Block 1 = Yes
Exit
Save

19. 1st LEVEL - PROCESS FILE #### PROCESS EDITOR (File ID)### (page-1)
File name;
1. Comment;
2. Alignment Sequence: 1st Mask or AGA ….
3. TTL Alignment Mode (none, I-line or HeNe/B2)
4. TV PA Measurement Mode;
#### PROCESS EDITOR (Reticle ID)### (page-2)
1. Reticle ID
#### PROCESS EDITOR (Fine Reticle Alignment)### (page-3)
1. Fine Align Tol xy = Theta =
Lmixed4X_nwell/PFmixed4X_nwell
anything you want, like: second level active
1st Mask
HeNe/B2 PA
Nwell
0.03 µm
0.03 µm
The Process file has 36 pages, only highlighted pages can be accessed, if AGA in item 2 page 2 is selected then page 4 is highlighted and gives row and column and x,y location of the prealignment marks. If alignment mode HeNe is selected page 13 gives the x&y coordinates of the fine alignment marks, if I-line was selected then pg 10&11give fine alignment mark locations, if 1st Mask is selected page 4 to 36 are bypassed.

20. 2ND 3RD 4TH LEVEL PROCESS FILE
This process file does alignment to 2 TVPA marks and then looks at 4 locations for fine alignment. It uses Broad-Band illumination and 20P-4F multi-marks.
Page –17
1. Number of sample shots (2,4,6,8,12,16)
Main; 4
Preliminary ; 4
2. AGA for first wafer ; AGA
AGA for 2nd and more wafer ; AGA
Page –19
Limit of x or y difference ; 0.5µm (default=0.2µm, can be as large as 9µm)
Page –1 Alignment Mode
2. Alignment Sequence Mode; AGA
3. TTL Alignment mode. ; HeNe-TV
4. TV PA Measurement Mode ; PA
Page –4
L) Shot : clm= ? row= ?
PA Mark Position; Xlp=QPAX mm Ylp= QPAY mm
R) Shot : clm= ? row= ?
PA Mark Position; Xrp=QPAX mm Yrp= QPAY mm
Page –13
AA Mark Position; B: X=BF2X mm Y = BF2Y mm
C: X=CF2X mm Y = CF2Y mm
Brot X=0 Y=0
AA Mark Pattern ; 20P-4F
Mark Condition ; Island
Wafer Surface Condition ; 0
Page –15
AA illumination Mode ; Mode-3
C1….
R1….

21. 2ND LEVEL OVERLAY VERIFICATION
Mixed Sub-CMOS Product

22. OVERLAY VERIFICATION FOR BIG CMOS
Level 4 VT
Level 3 Stop
Level 2 Active

23. EXAMPLE FILE NAMES Small (< 8mm) CMOS Chips
Stepper Job
Layout File
Shot File
Process File
Reticle Table
Reticle ID
mixed4x1_nwell
Lmixed4x1_nwell
Smixed4x1_nwell
Pmixed4x1_nwell
Rmixed4x
Mixed4x1
Mixed4x1_act
Lmixed4x1_act
Smixed4x1_act
Pmixed4x1_act
Mixed4x1_stop
Lmixed4x1_stop
Smixed4x1_stop
Pmixed4x1_stop
Mixed4x1_vt
Lmixed4x1_vt
Smixed4x1_vt
Pmixed4x1_vt
Mixed4x1_poly
Lmixed4x1_poly
Smixed4x1_poly
Pmixed4x1_poly
Note: mixed4x1_nwell is 1st level no alignment, quadrant 2
and Mixed4x1_poly is level 5, 9 etc., with alignment, quadrant 2

24. EXAMPLE FILE NAMES Metal Gate PMOS and Shortcourse Jobs
Stepper Job
Layout File
Shot File
Process File
Reticle Table
Reticle ID
L082SHORT4X_DIFF
S082SHORT4X_DIFF
P082SHORT4X_DIFF
Rmixed4x
Mixed4x1
L082SHORT4X_OX
S082SHORT4X_OX
P082SHORT4X_OX
Mixed4x2
L082SHORT4X_CC
S082SHORT4X_CC
P082SHORT4X_CC
Mixed4x3
L082SHORT4X_M
S082SHORT4X_M
P082SHORT4X_M
Mixed4x4
END
Note: L082SHORT4X_DIFF is 1st level no alignment, quadrant 2

25. EXAMPLE FILE NAMES Large (< 10mm) CMOS Chips
Stepper Job
Layout File
Shot File
Process File
Reticle Table
Reticle ID
F083ADC_nwell
LF083ADC_nwell
SF083ADC_nwell
PF083ADC_nwell
Rmixed4x
Mixed4x1
F083ADC_act
LF083ADC_act
SF083ADC_act
PF083ADC_act
Mixed4x2
F083ADC_stop
LF083ADC_stop
SF083ADC_stop
PF083ADC_stop
Mixed4x3
F083ADC_vt
LF083ADC_vt
SF083ADC_vt
PF083ADC_vt
Mixed4x4
F083ADC_poly
LF083ADC_poly
SF083ADC_poly
PF083ADC_poly
Note: F083ADC _nwell is 1st level no alignment, quadrant 2
and F083ADC _poly is level 5, 9 etc., with alignment, quadrant 2

26. /shared/cmostestchip2007/CMOS4XTEMPLATE
9.8mm X 9.8mm CHIP TEMPLATE
Template for
CMOS4Xdesigns
Each cell is 800 µm x 800µm
Entire Chip is 9800µm x 9800µm
Lower Half has Process Verification Test Structures.
There is a 200µm street between quadrants on the testchip
This is the largest chip that can have 4 masks per plate.
/shared/cmostestchip2007/CMOS4XTEMPLATE

27. EXAMPLE OF A MEBES PLOT JOB
12 cm
2/25/09 9:12:23 MEBES 967
REV, 4.6
SPECIFICATION FILE: JOB:SHORT.JB
DTITLE: CMOS FOUR LEVELS / PLATE
ITITLE: BARCODE
MTITLE: LEVELS 1,2,3,4
CASSETTE TYPE ID:14
LEVEL PLOTTED: 1
JOB SCALE: 1
JOB SCALE:
ADDRESSING: MICRONS
PLOT SCALE: 1.00 TO 1 CM
ID PATTERN X DIMENSION Y DIMENSION PLACEMENT ORIENTATION TONE
1. NWELL UNMIRROR UNMIRROR NORMAL
2. ACTIVE UNMIRROR UNMIRROR NORMAL
3. STOP UNMIRROR UNMIRROR NORMAL
4. VT UNMIRROR UNMIRROR NORMAL
LAYER 1,2,3,4 CMOS 4 LEVELS / PLATE
LVL 1
LVL 4
Y Axis
LVL 2
LVL 3
BARCODE
0.0
0.0
X Axis
12 cm

28. CREATE A MEBES JOB DECK SLICE EDIT, 14 14 means 5” by 5” glass
OPTION AA=0.5, BA=0.5, PA, SA=250, VA=10
REPEAT A, 10
STITLE A, 10000, 10000, MEBES III
MTITLE 1, NWELL
MTITLE 2, ACTIVE
MTITLE 3, STOP
MTITLE 4, PMOS VT
MTITLE 5, POLY
MTITLE 6, LDD N
MTITLE 7, LDD P
MTITLE 8, N DS
MTITLE 9, P DS
MTITLE 10, CONTACT
MTITLE 11, METAL
DTITLE A, SUBMICRON CMOS
CHIP 1,(A,RITLOGO-50-01)
ROWS 10000/63500
CHIP 2,(A,FIDUCIA-LS-01)
ROWS 63500/63500
CHIP 3,
$ (1R,EMCR ),
$ (2,EMCR ),
$ (3,EMCR ),
$ (4,EMCR ),
$ (5,EMCR ),
$ (6,EMCR ),
$ (7,EMCR ),
$ (8,EMCR ),
$ (9,EMCR ),
$ (10,EMCR ),
$ (11,EMCR )
END
SLICE EDIT, 14
14 means 5” by 5” glass
OPTICON AA=0.5, BA=0.5, PA, SA=40, VA=10
AA means address all levels = 0.5 µm
BA means beam size all levels = 0.5 µm
PA means all levels positive resist
SA means all levels spot current 40 nA
VA means all levels acceleration = 10KV
MTITLE 1, ADV-CMOS STI
DTITLE A, RIT EMCR650
ITITLE A, BARCODE
ORIENT A, ITITLE, TITLEROT=90, LOC=
CHIP1, (1,cmostestchip-LVL-01, RC=15),
first level of cmostestchip maskset
END

29. REFERENCES Robert Manley process improvement project.
Germain Fenger process improvement project.
3. Fuller, Lynn Introduction to Reduction Steppers. Rochester Institute of Technology, 2002
4. FPA-200i1 Maintenance Training: Basic Operations Manual, Canon USA
Chuck Smith, MicroE Alumni 1987, Applications Engineer,
Canon USA, Inc x203,
Bill Cooman, Canon Equipment Engineer, Maintains the RIT
Canon FPA 2000-i1