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Anshul Kumar, CSE IITD CSL718 : Main Memory 6th Mar, 2006.

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Presentation on theme: "Anshul Kumar, CSE IITD CSL718 : Main Memory 6th Mar, 2006."— Presentation transcript:

1 Anshul Kumar, CSE IITD CSL718 : Main Memory 6th Mar, 2006

2 Anshul Kumar, CSE IITD slide 2 RequirementsRequirements CPU – Main Memory : word transfers Cache – Main Memory : block/line transfers (words also in WT) I/O – Main Memory : large block transfers Use of write buffers Out of order execution How to speed-up transfer?

3 Anshul Kumar, CSE IITD slide 3 Use Wider Bus Wide bus between cache and main memory – Multiple words transferred in parallel CPUCache Memory

4 Anshul Kumar, CSE IITD slide 4 Use Faster Bus Improve the throughput, not necessarily the latency first word subsequent words latency

5 Anshul Kumar, CSE IITD slide 5 Interleaved Memory CPUCache Memory bank 0bank 1bank 2bank 3

6 Anshul Kumar, CSE IITD slide 6 Interleaved Memory Performance Given : L=line size m=number of interleaved modules T a =memory access time T c =memory cycle time T bus =bus cycle time Find : T line =line access time

7 Anshul Kumar, CSE IITD slide 7 Case I first word subsequent L -1 words TaTa T bus

8 Anshul Kumar, CSE IITD slide 8 Case II first m words TaTa m. T bus next m words m. T bus TcTc

9 Anshul Kumar, CSE IITD slide 9 Case III TaTa TcTc T bus TcTc TcTc

10 Anshul Kumar, CSE IITD slide 10 Semiconductor Memory Technology Fast memory for cache - Static RAM (SRAM) High density main memory - Dynamic RAM (DRAM) Non volatile memories for embedded systems - ROM, PROM, EPROM, Flash

11 Anshul Kumar, CSE IITD slide 11 DRAM Structure Storage cells Sense amps Column decoder Column address CAS Address pins Row address RAS WE 2n2n 2 n/2 RowdecoderRowdecoder D in D out

12 Anshul Kumar, CSE IITD slide 12 Enhancing DRAM Performance Multiple arrays of cells Access multiple bits in a row (sequentially | randomly) Synchronous interface rather than asynchronous interface Transfer data on both edges of clock

13 Anshul Kumar, CSE IITD slide 13 DRAM Technologies Fast Page Mode (FPM) DRAM Extended Data Out (EDO) DRAM Burst Extended Data Out (BEDO) DRAM Synchronous DRAM (SDRAM) Synchronous-Link DRAM (SLDRAM) Double Data Rate SDRAM (DDR SDRAM) Direct Rambus DRAM (DRDRAM) Video RAM (VRAM) – dual ported

14 Anshul Kumar, CSE IITD slide 14 Memory Modules in PCs SIMM (single in-line memory module): Have 72 or 30 pins. Support 32-bit and 16-bit data transfers. DIMM (dual in-line memory module): Have 168 pins. Support 64-bit data transfers.

15 Anshul Kumar, CSE IITD slide 15 Fast Page Mode (FPM) DRAM Row address selects a page (row) Bits in a page selected by column addresses

16 Anshul Kumar, CSE IITD slide 16 Extended Data Out (EDO) DRAM extends the time for which output data is valid, easing timing issues between the CPU and RAM and enhancing performance

17 Anshul Kumar, CSE IITD slide 17 Burst EDO (BEDO) DRAM A variant on EDO DRAM Read or write cycles are batched in bursts of four Two LSBs of the column address get modified internally to produce each address of the burst sequence

18 Anshul Kumar, CSE IITD slide 18 SDRAMSDRAM Synchronizes itself with the CPU's bus One block of data can be sent to the CPU while another is being prepared for access About three times faster than conventional FPM RAM and about twice as fast EDO DRAM and BEDO DRAM Standards : PC66, PC100, PC133, PC150 (PC150 means 150 MHz, peak bandwidth upto 1.2GB/s) DDRSDRAM : PC1600, PC2100, PC2700, PC3200 – figure refers to MB/s

19 Anshul Kumar, CSE IITD slide 19 SDRAM Organization

20 Anshul Kumar, CSE IITD slide 20 RDRAMRDRAM Highest bandwidth per pin A highly efficient packet-based protocol, pipelined command and data, low-voltage signaling and precise clocking to minimize skew between clock and data lines densities up to 256Mbit speeds from 800MHz to 1200MHz single-, dual- or quad-channel RIMM modules to support bandwidths from 1.6 GB/sec to 10.7 GB/sec and system memory capacities up to 8GB Match Pentium 4’s system bus : 400/533MHz

21 Anshul Kumar, CSE IITD slide 21 RDRAM Organization

22 Anshul Kumar, CSE IITD slide 22 RIMMRIMM

23 Anshul Kumar, CSE IITD slide 23 Comparison of some DRAMs Memory Typical System Ideal Timing Usual DRAM Technology Bus Speeds Speed (ns) DRAM or worse FPM EDO BEDO SDRAM (PC100)

24 Anshul Kumar, CSE IITD slide 24 Fast Page Mode DRAM

25 Anshul Kumar, CSE IITD slide 25 Interleaving with Fast Page Mode

26 Anshul Kumar, CSE IITD slide 26 ReferencesReferences Flynn’s Book Hennessy & Patterson’s Book


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