# Digital Testing: Current Testing

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Digital Testing: Current Testing
4/13/2017 Based on text by S. Mourad "Priciples of Electronic Systems"

Problem 1 a) Use Boolean difference to find all tests for E s-a-1 and Es-a-0 fault. b) Find all tests that distinguish between E s-a-0 and D s-a-1 faults.

Problem 2 For the circuit shown compute the combinational controllability and observability in all the signal lines. Use the following notation (CC0,CC1)CO to indicate your results. For instance, if the signal x1 has CC0=1, CC1=1 and CO=5, write (1,1)5 next to the signal name on the figure. Make sure that you consider all signals (including the branch signals a,b,c,d,e, and f).

Problem 3 Use the critical signal approach to detect C s-a-1 fault. What other faults can you detect using this run of the critical signal setting? Hint: start with the output signal Y = 1. ABCDEFGH Y

Problem 4 Use D-algorithm to find test vector for s-a-0 fault on the fanout branch h in the circuit shown.

Outline Why current testing Effect on propagation delays Measurement of current Test pattern generation Subthreshold current Effect of deep submicron From Fab. 2, 2001 Copyrights(c) 2001, Samiha Mourad

Motivation Early 1990’s – Fabrication Line had 50 to 1000 defects per million chips Conventional way to reduce defects: Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness New way to reduce defects: IDDQ Testing – also useful for Failure Effect Analysis

What is Current Testing?
Also called IDDQ Testing Measurement of the supply, VDD, quiescent current the sum of all off-state transistors Useful only for CMOS circuits Limitation due to shrinking technology

Basic Principle of IDDQ Testing
Measure IDDQ current through Vss bus

Current Testing Basics
CMOS circuits operate with normally negligible static current (power) But, a defect that causes an appreciable static current can be detected by measuring the supply current, IDDQ Technique used since inception of CMOS technology Limitation due to shrinking technology

IDDQ Testing IDD --- Current flow through VDD Q --- Quiescent state
IDDQ Testing --- Detecting faults by monitoring IDDQ VDD IDD Inputs CMOS circuit Outputs In general a CMOS circuit consumes very small steady state current. Many CMOS faults result in large IDDQ , typically ranged from tens of mA to mA. Normal IDDQ: ~10-9Amp. Abnormal IDDQ: >10-5Amp.

Fault effect is easy to detect Many realistic faults are detectable ATPG is relatively simple Test length is shorter Built-in current sensing is possible Large difference between faulty and fault free circuit. Faults detectable include bridging, break, transistor stuck-on, gate-oxide short, latch-up , etc.. No fault propagation is needed. Many built-in current sensors have been developed.

IDDQ Distribution (Md - Mg) should be an easily measurable quantity Mg
Frequency Good Defective Mg Md IDDQ (Md - Mg) should be an easily measurable quantity

How Does it Work? Apply a test pattern
Wait for the transient to settle down Measure the current Needed: How to generate the patterns How to measure the current But, first current characteristics

Dynamic Current

Inverter: Good and Faulty IDDQ

A NAND Tree Measurement requires the current settling down
The effect of the delays shown on the next slide

Current for the NAND Tree

IDDQ Measurement Measurement may interfere with the measured current
A successful measurement should be: easily placed between the CUT and the bypass Capacitor of the power pin Capable of measuring small currents Non intrusive, no drop of VDD Fast measurement few ns per pattern Two types: on- and off-chip

External Measurement Problem: CUT sensitive to power supply drop on R

Current Sensing Structures
Power Supply CUT R ( a ) ( b ) Sense amplifiers designed to minimize the VDD voltage drop Shunting by diode limits the voltage drop to 0.7V Another option is to use pass transistor

Internal Measurement I IC V
When large IDDQ exists, V>VR and Fail flag is set. VDD-GND Shorts Bridging Faults Gate oxide pinholes Floating gates & junction leakages No defect V GND I ref No defect Defect (b) DUT V.drop Comparator IC dd (a)

BICS Based on Bipolar Transistor
CMOS Module VDD + - GND I V VR Pass/Fail Flag VR VDD f1 f2 CMOS Module Virtual Ground Switching circuit V V Fault categories The switching circuit may switch off a faulty module to prevent large power consumption The first design for BICS. The sensing device is a bipolar transistor which has the property that when I is small, dV/dI is large, hence can give good current resolution. When I is large, dV/dI is small, then V is limited. The basic idea is to compare the voltage drop on the bipolar transistor with a reference voltage VR and use a differential amplifier to provide the error indication. When an excess current exists, the Pass/Fail flag is set, and the switching circuit will turn off the bipolar transistor to prevent further current consumption. Bipolar or lateral NPN process is needed.

Analysis of a Short Consider p-MOS with input B stuck-on (B s/0)
Transistor is always on For the shorted pMOS transistor, find: a path form VDD to GND through this transistor, then AB = 11 is needed to detect this short using IDDQ

Detecting Short Faults
To detect leakage between gate and source B set A=0 and C=1 To detect leakage between gate and drain B set A=1 and C=0

Test Pattern Generation (TPG)
Mainly two methods: based on switch level using graph representation as for layout based on leakage fault models

Graph or Switch Based TPG
Path A,A,B to test shorts on A transistors Path B,A,B to test shorts on B transistors

Leakage Fault Model pMOS model
sg dg bd sd bs bg Assuming all possible shorts between the four nodes, bulk, source, gate, and drain results in 6 tuples of faults (bg bd bs ds gd gs ) Consider various I/O patterns Only correct logic signal values are used for leakage models. Some I/O combinations are impossible for a given logic, for instance 00, 11 The 6 tuples are represented by octal numbers as shown in column N of the table For instance for I/O=10 transistor fault code is N=438=100011 and represents the following faults: bg, gd, gs IO bg bd bs ds gd gs N n y n n y n 22 y n n n y y 43 pMOS model

Characterizing a NAND The leakage fault model notation is used to characterize a 2-input NAND Octal fault vector code for each transistor I/O octal code, eg.: 6=110=>A=1,B=1,O=0

Characterizing a NOR

IDDQ Vector Selection Characterize each logic component using switch-level simulation – relate input/output logic values & internal states to: leakage fault detection weak fault sensitization and propagation Store information in leakage and weak fault tables Generate complete stuck-at fault tests Logic simulate stuck-at fault tests – use tables to find faults detected by each vector to select vectors for current measurement

Impact of Deep Submicron
Deep submicron transistors work at lower Vt The lower Vt the higher IDDQ The discrepancy between the faulty and non-faulty IDDQ is narrowing

Controlling leakage IDDQ
Reverse biasing the substrate Cooling the devices Using dual threshold voltage Partitioning the circuit to manageable IDDQ

Change of Current with Body Bias and Temperature

Stuck-open Faults To test a/1 use vectors A stuck open transistor
is always off A B C D Out T1 = T2 = ? A D x B y C Out When T2 is applied (and transistor A is open), charge sharing among x, y and Out occurs, and logic state is undetermined. Yet the following inverter will draw a significant current and IDDQ detects this fault. A To detect A stuck-open , we need two vectors, the first one setting output o to logic 0 and the second one trying to set up a conducting path that must go though A such that in the fault-free circuit , o become 1 and in the faulty circuit o retains o. T1 and T2 are two vectors that satisfy the above condition. However it is possible that due to charge sharing the voltage value at o become an intermediate voltage in the faulty circuit and hence logic testing can not detect this fault. Fortunately if IDDQ testing is available, this fault can still be detected. B C D

Other Faults Detectable by IDDQ
Gate-oxide short Most stuck-at faults Latch-up Delay faults Any other fault due to extra conductor, missing isolating layer, excess well/substrate leakage, etc. Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.

Circuit Constraints To ensure IDDQ detectability, two conditions must be satisfied: 1. Normal IDDQ must be small 2. Faults must result in large IDDQ Though many faults are IDDQ detectable, we still have to be very carefully when employing this method. In the following, several examples indicating the problems are given.

A Good Circuit that may be Problem due to high impedance node
identified as Faulty x=11? z=x0? 1 MUX Output Sel=0 if AB=10 A=011 B=110 large current Due to some don't care terms in the function to be designed , a designer may consider the circuit to be correct. However leakage current may occur during normal operation. When the third pattern AB=10 is applied, change sharing between x, z occurs, and a large current may exist in the inverter. However the output is still correct. Problem due to high impedance node

that cannot be Detected by IDDQ Problem due to feedback loop
A bridging fault (BF) that cannot be Detected by IDDQ F a x b y 1 To detect BF (x, y), different logic values must be applied to x and y, respectively. Due to the self control loop, either x dominates y or y dominates x. Eventually either (x, y)=(1, 1) or (x, y)= (0,0). =1: a=0, b=1 =1: Eventually x=y (and will set to full VDD or GND value as one signal will dominate), no big current Problem due to feedback loop

Problems with Dynamic Logic
f o a f O p x Inputs y f b Left side is a typical domino logic gate with a precharge input f. During the evaluation phase, if the precharge node is not connected to ground, then it should retain at 1. However due to charge sharing, it can become an intermediate voltage and hence large current may occur in the inverter. A BF(x, y) inside the n-block is not IDDQ testable because they can never be connected to VDD and Ground simultaneously. Similarly if x is in one n-block and y is in another, the BF(x, y) is not IDDQ testable. A BF between the output of two inverter such as (a, b) in the right figure is IDDQ detectable. However if another undetectable BF(o, p) exists then the fault detection may be invalidated. Problems: 1. Large current in normal circuits due to charge sharing 2. Very few faults are detected because of the precharge property (no direct path VDD-GND) 3. Fault masking of BF(a, b) due to BF(o, p)

Transistor Group G3 Output G2 Transistor group (TG) --- "Channel-connected component" Connections between two TGs are unidirectional Control direction or loop can be defined A B G1 From the above examples, it becomes clear that one must be very careful when using IDDQ testing. A set of design & test rules for IDDQ testing was derived by Lee & Breure in T-CAD'92. To understand these rules, an important concept called transistor grouping must be introduced first. A transistor group is a set of transistors whose channels are connected through drain or source without passing though VDD or GND. After partitioning, the I/O between TGs can be defined by their gate terminal connections, e.g., G2 is an input to G3 and G1 is an input to G2. Through these I/O relationship, control direction or loop can be defined. The concept of TG is widely used in switch level analysis of CMOS circuits. C E D

A Minimum Set of Design & Test Rule for IDDQ Testing
A1. Gate and drain (or source) nodes of a transistor are not in the same TG. A2. No conducting path exists from VDD to GND during steady state. A3. Each output of a TG is connected to VDD or GND during steady state. A4. No control loops among TGs exist. A5. The bulk (or well) of an n-(p-)type transistor is connected to GND (VDD). A6. During testing, each PI is controlled by a monitored power source. A1 is used to prevent "self control". A5 is used to prevent "anomalous reverse conducting" effect. See Rajsuman DAC'87 for details. A6 is because a current sensor usually only monitors the VDD line or GND line , but not both. Hence a large current through PI may flow through a power line that is not monitored.

Results of Design & Test Rules
Theorem 1: All irredundant single BFs in a circuit satisfying A1-A6 can be detected using IDDQ testing. Theorem 2: For a circuit satisfying A1-A6, a test detecting a single BF f also detects all multiple BFs that contain f. Theorem 3: If any one of A1-A6 is removed, then circuits exist for which IDDQ testing cannot give correct test results. Strategies for dealing with circuits not satisfying each rule are required to ensure IDDQ detectability. The three theorems are self-explanary. It must be pointed out that the set of rules is sufficient, but not necessary. This is because one may have a circuit that does not satisfy some rule, but is still IDDQ testable, e.g., a cross coupled 6-transistor XOR gate. The set of rules is minimum in the sense that if any of the rules is removed, then problems exist for some circuits, not for all circuit.

Fault Simulation in IDDQ
1. Fault models --- Bridging, break, stuck-open, stuck-at ? 2. Fault list generation --- need inductive fault analysis 3. Fault coverage ? 4. Easy for bridging and stuck-on faults 5. Difficult for break and stuck-open faults 6. Stuck-at faults may or may not be modeled as short to VDD or GND The conventional fault coverage concept based on single stuck at faults may need some modifications---IFA is important. Break detection is an important but difficult research topic.

Fault simulation for BFs
If A1-A6 are satisfied, then fault simulation is quite simple 1. Perform a good circuit simulation for the given test pattern. 2. Any BF between a node with logic 1 and a node with logic 0 is detected. No simulation on faulty circuit is needed. No fault list enumeration is needed. One test vector divides the circuit nodes into two sets, one with logic 1 and the other with logic 0. Any fault between two nodes in different sets is detected. Two test vectors divide the circuit nodes into 4 sets with logic values of 00, 01, 10, 11, respectively. A BF between nodes from any two different sets is detected. Therefore if a test set can distinguish all circuit nodes, the all BFs are detected. => No fault list enumeration is needed.

Test Generation 1. Conventional test generation for stuck-at faults can be modified to detect BFs. 2. No fault propagation. 3. Must make sure the faults result in a conducting path between VDD and GND Switch level test generation may be necessary. 4. Break and stuck-open faults are difficult to detect. self-explanary

Test generator for bridging faults
Again, assume A1-A6 are satisfied 1. For the bridging fault BF (a, b) to be detected, add an XOR gate with its inputs connected to a and b. 2. The test generator work is simply to set the output of the XOR gate to 1. No Fault propagation. self-explanary

Current monitoring Techniques
ATE ATE Current Supply Monitor BICS DUT DUT CUT The most important work in IDDQ testing may be the design of current sensors. There exist three methods. External monitoring Test Fixture Built-In Current Sensor

External Devices Transistor conducts in normal mode and
TEST POWER SUPPLY S (STROBE) N CN IDD DUT VSS pin VDD pin VDD RM Transistor conducts in normal mode and is open in test mode During normal mode, S turns on the transistor. During test mode, the transistor is off and all current flows through RM. Hence by measuring the voltage drop on RM, the fault effect can be identified. Current resolution is limited because the current of the whole chip must be measured. Existing ATE may have no current sensing capability. Current measurement is usually slow. Mixed-type circuits such as BiCMOS are not easy to applied because Bipolar and CMOS consume different ranges of steady state current. Problems: 1. Current resolution is limited Test equipment must be modified Current cannot be measured at the full speed of the tester Cannot partition circuit.

Built-in Current Sensors (BICSs)
VDD BICS CUT Test Pass /Fail VDD Inputs Outputs Inputs CUT Outputs OR Test BICS Pass /Fail A BICS can be placed at the VDD line or GND line. Sometimes called ISSQ testing

BICS Based on Logic Threshold
Favalli (JSSC-90) Pull- up Pull- down MT t Gnd MTD tout VDD inputs ... Normal : t = 1 Test : t = 0 For correct operation No path to VDD from gates of MTD transistors tout = 1 if no fault = 0 if fault exists Two transistors are added to each logic gate. Hence overhead is large.

Improvement on Favalli's design
Pull- up Pull- down MT MTD Gnd tout VDD inputs ... t Merge all MT and MTD respectively Though the number of transistors is reduced, the total area overhead may not be saved as much because the same current supply (or sink) capacity is required.

Improvement on Favalli's Design
VDD VDD VDD Pull- up Pull- up Pull- up inputs ... Pull- down Pull- down Pull- down ... self-explanary MT tout Using BiCMOS design MTD Gnd

BICS Based on Dual Power Supply & Operational Amplifier
VDD'=5V RS IRS - Virtual Short I- + Vout+ Vout- I+ VDD=3V IDD VSS Vin=3V Threshold detector CUT VDD is provided by the OP amplifier which is powered by a higher level. The current through Rs is equal to IDD. VDD=Vin, hence very low performance degradation can be achieved. Fault indication Virtual short VDD~Vin Infinite input impedance of OP I-=0 and IRS=IDD

BICS Based on Current Conveyor
Iz Virtual Short Current Conveyor Iy V'DD=5V Threshold Detector Ix VDD Fail/Pass CUT The current conveyor conveys Ix to Iy for fault effect identification. Virtual short VDD ~ VDD' Current Conveying Iy ~ Ix

Advantages of Built-In Current Sensors (BICS)
Higher test rate compared to external devices Easier to partition circuits Easier to control current resolution Suitable for mixed-mode circuits Built-In self test capability achievable Lower test equipment cost On-Line testing possible self-explanary

Disadvantages of BICS Impact on circuit performance
Reliability of itself Area overhead Power consumption A BICS may cause extra circuit delay due to the reduced VDD level. If a BICS is faulty, then the whole circuit may crash. Large power consumption due to analog design such as op and differential amp, etc.

HP and Sandia Lab Data HP – static CMOS standard cell, 8577 gates, 436 FF Sandia Laboratories – 5000 static RAM tests Reject ratio (%) for various tests: Reject ratio (%) Company HP Sandia No Test 16.46 0.80 Only Funct. 6.36 0.09 Only Scan 6.04 0.11 IDDQ Without IDDQ With IDDQ Both 5.80 0.00 Functional Tests 5.562

Failure Distribution in Hewlett-Packard Chip

Sematech Study IBM Graphics controller chip – CMOS ASIC, 166,000 standard cells 0.8μ static CMOS, 0.45μ lines (Leff), 40 to 50 MHz clock, 3 metal layers, 2 clocks Full boundary scan on chip Tests: Scan flush – 25 ns latch-to-latch delay test 99.7 % scan-based stuck-at faults (slow 400 ns rate) 52 % SAF coverage functional tests (manually created) 90 % transition delay fault coverage tests 96 % pseudo-stuck-at fault coverage IDDQ tests

Sematech Conclusions Hard to find point differentiating good and bad devices for IDDQ & delay tests High # passed functional test, failed all others High # passed all tests, failed IDDQ > 5 mA Large # passed stuck-at and functional tests Failed delay & IDDQ tests Large # failed stuck-at & delay tests Passed IDDQ & functional tests Delay test caught failures in chips at higher temperature burn-in – chips passed at lower temperature

Current Limit Setting Should try to get it < 1 mA
Histogram for 32 bit microprocessor

Delta IDDQ Testing (Thibeault)
Use derivative of IDDQ at test vector i as current signature ΔIDDQ (i) = IDDQ (i) – IDDQ (i – 1) Leads to a narrower histogram Eliminates variation between chips and between wafers Select decision threshold Δdef to minimize probability of false test decisions

|IDDQ| and |DIDDQ|

Setting Threshold IDDQ ΔIDDQ Mean (good chips) 0.696 μA -2×10-4 μA
Mean (bad chips) 1.096 μA 0.4 μA Variance 0.039 (μA)2 0.004 (μA)2 Δdef Error Prob. 0.3 0.059 7.3×10-4 0.4 0.032 4.4×10-5 0.5 0.017 1.7×10-6

Summary IDDQ test is used as a reliability screen
Can be a possible replacement for expensive burn-in test IDDQ test method has difficulties in testing of sub-micron devices Greater leakage currents of MOSFETs Harder to discriminate elevated IDDQ from 100,000 transistor leakage currents ΔIDDQ test may be a better choice Built-in current (BIC) sensors can be useful