Presentation on theme: "4/28/2015 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Current Testing."— Presentation transcript:
4/28/2015 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Current Testing
Problem 1 a) Use Boolean difference to find all tests for E s-a-1 and Es- a-0 fault. b) Find all tests that distinguish between E s-a-0 and D s-a- 1 faults.
Problem 2 For the circuit shown compute the combinational controllability and observability in all the signal lines. Use the following notation (CC0,CC1)CO to indicate your results. For instance, if the signal x1 has CC0=1, CC1=1 and CO=5, write (1,1)5 next to the signal name on the figure. Make sure that you consider all signals (including the branch signals a,b,c,d,e, and f).
Problem 3 Use the critical signal approach to detect C s-a-1 fault. What other faults can you detect using this run of the critical signal setting? Hint: start with the output signal Y = 1. ABCDEFGH Y
Problem 4 Use D-algorithm to find test vector for s-a-0 fault on the fanout branch h in the circuit shown.
Fab. 2, 2001Copyrights(c) 2001, Samiha Mourad6 Outline Why current testing Effect on propagation delays Measurement of current Test pattern generation Subthreshold current Effect of deep submicron From
Motivation Early 1990’s – Fabrication Line had 50 to 1000 defects per million chips Conventional way to reduce defects: Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness New way to reduce defects: I DDQ Testing – also useful for Failure Effect Analysis
What is Current Testing? Also called I DDQ Testing Measurement of the supply, V DD, quiescent current the sum of all off-state transistors Useful only for CMOS circuits Limitation due to shrinking technology
Basic Principle of I DDQ Testing Measure I DDQ current through V ss bus
Current Testing Basics CMOS circuits operate with normally negligible static current (power) But, a defect that causes an appreciable static current can be detected by measuring the supply current, I DDQ Technique used since inception of CMOS technology Limitation due to shrinking technology
IDDQ Testing IDD --- Current flow through VDD Q --- Quiescent state IDDQ Testing --- Detecting faults by monitoring IDDQ Normal IDDQ: ~10 -9 Amp. Abnormal IDDQ: >10 -5 Amp. CMOS circuit Inputs Outputs VDD IDD
Advantages of IDDQ Testing Fault effect is easy to detect Many realistic faults are detectable ATPG is relatively simple Test length is shorter Built-in current sensing is possible
I DDQ Distribution MgMd IDDQ Defective Good Frequency (Md - Mg) should be an easily measurable quantity
How Does it Work? Apply a test pattern Wait for the transient to settle down Measure the current Needed: How to generate the patterns How to measure the current But, first current characteristics
Inverter: Good and Faulty I DDQ
A NAND Tree Measurement requires the current settling down The effect of the delays shown on the next slide
Current for the NAND Tree
IDDQ Measurement Measurement may interfere with the measured current A successful measurement should be: easily placed between the CUT and the bypass Capacitor of the power pin Capable of measuring small currents Non intrusive, no drop of VDD Fast measurement few ns per pattern Two types: on- and off-chip
External Measurement Problem: CUT sensitive to power supply drop on R
Current Sensing Structures Sense amplifiers designed to minimize the VDD voltage drop Shunting by diode limits the voltage drop to 0.7V Another option is to use pass transistor Power Supply CUT R ( a ) ( b ) R R
Internal Measurement VDD-GND Shorts Bridging Faults Gate oxide pinholes Floating gates & junction leakages No defect V GND I V ref No defect Defect (b) DUT V.drop V ref Comparator IC V dd GND (a) V GND When large IDDQ exists, V>V R and Fail flag is set.
BICS Based on Bipolar Transistor Pass/Fail Flag VRVR VDD CMOS Module Virtual Ground Switching circuit CMOS Module VDD + - GND I V VRVR The switching circuit may switch off a faulty module to prevent large power consumption V V Fault categories
Analysis of a Short For the shorted pMOS transistor, find: a path form V DD to G ND through this transistor, then AB = 11 is needed to detect this short using I DDQ Consider p-MOS with input B stuck-on (B s/0) Transistor is always on
Detecting Short Faults a)To detect leakage between gate and source B set A=0 and C=1 b)To detect leakage between gate and drain B set A=1 and C=0
Test Pattern Generation (TPG) Mainly two methods: based on switch level using graph representation as for layout based on leakage fault models
Graph or Switch Based TPG Path A,A,B to test shorts on A transistors Path B,A,B to test shorts on B transistors
Leakage Fault Model IO bg bd bs ds gd gs N n y n n y n y n n n y y Assuming all possible shorts between the four nodes, bulk, source, gate, and drain results in 6 tuples of faults (bg bd bs ds gd gs ) Consider various I/O patterns Only correct logic signal values are used for leakage models. Some I/O combinations are impossible for a given logic, for instance 00, 11 The 6 tuples are represented by octal numbers as shown in column N of the table For instance for I/O=10 transistor fault code is N=43 8 = and represents the following faults: bg, gd, gs sg dg bd sd bs bg pMOS model
Characterizing a NAND I/O octal code, eg.: 6=110=>A=1,B=1,O=0 Octal fault vector code for each transistor The leakage fault model notation is used to characterize a 2-input NAND
Characterizing a NOR
I DDQ Vector Selection Characterize each logic component using switch-level simulation – relate input/output logic values & internal states to: leakage fault detection weak fault sensitization and propagation Store information in leakage and weak fault tables Generate complete stuck-at fault tests Logic simulate stuck-at fault tests – use tables to find faults detected by each vector to select vectors for current measurement
Impact of Deep Submicron Deep submicron transistors work at lower Vt The lower Vt the higher IDDQ The discrepancy between the faulty and non-faulty IDDQ is narrowing
Controlling leakage I DDQ Reverse biasing the substrate Cooling the devices Using dual threshold voltage Partitioning the circuit to manageable I DDQ
Change of Current with Body Bias and Temperature
Stuck-open Faults ABCDOut T1 =11110 T2 =0001? When T2 is applied (and transistor A is open), charge sharing among x, y and Out occurs, and logic state is undetermined. Yet the following inverter will draw a significant current and IDDQ detects this fault. B C x y D Out CB A D A To test a/1 use vectors A stuck open transistor is always off
Other Faults Detectable by IDDQ Gate-oxide short Most stuck-at faults Latch-up Delay faults Any other fault due to extra conductor, missing isolating layer, excess well/substrate leakage, etc.
Circuit Constraints To ensure IDDQ detectability, two conditions must be satisfied: 1. Normal IDDQ must be small 2. Faults must result in large IDDQ
A Good Circuit that may be identified as Faulty Problem due to high impedance node When the third pattern AB=10 is applied, change sharing between x, z occurs, and a large current may exist in the inverter. However the output is still correct. x=11? z=x0? 1 MUX 0 Output Sel=0 if AB=10 A=011 B=110 large current
A bridging fault (BF) that cannot be Detected by IDDQ Problem due to feedback loop =1: a=0, b=1 =1: Eventually x=y (and will set to full VDD or GND value as one signal will dominate), no big current
Problems with Dynamic Logic Problems: 1. Large current in normal circuits due to charge sharing 2. Very few faults are detected because of the precharge property ( no direct path VDD-GND) 3. Fault masking of BF(a, b) due to BF(o, p) Inputs x y oa b p O
Transistor Group Transistor group (TG) --- "Channel-connected component" Connections between two TGs are unidirectional Control direction or loop can be defined A B C D Output G3 G2 G1 E
A Minimum Set of Design & Test Rule for IDDQ Testing A1. Gate and drain (or source) nodes of a transistor are not in the same TG. A2. No conducting path exists from VDD to GND during steady state. A3. Each output of a TG is connected to VDD or GND during steady state. A4. No control loops among TGs exist. A5. The bulk (or well) of an n-(p-)type transistor is connected to GND (VDD). A6. During testing, each PI is controlled by a monitored power source.
Results of Design & Test Rules Theorem 1: All irredundant single BFs in a circuit satisfying A1-A6 can be detected using IDDQ testing. Theorem 2: For a circuit satisfying A1-A6, a test detecting a single BF f also detects all multiple BFs that contain f. Theorem 3: If any one of A1-A6 is removed, then circuits exist for which IDDQ testing cannot give correct test results. Strategies for dealing with circuits not satisfying each rule are required to ensure IDDQ detectability.
Fault Simulation in IDDQ 1. Fault models --- Bridging, break, stuck-open, stuck-at ? 2. Fault list generation --- need inductive fault analysis 3. Fault coverage ? 4. Easy for bridging and stuck-on faults 5. Difficult for break and stuck-open faults 6. Stuck-at faults may or may not be modeled as short to VDD or GND
Fault simulation for BFs If A1-A6 are satisfied, then fault simulation is quite simple 1. Perform a good circuit simulation for the given test pattern. 2. Any BF between a node with logic 1 and a node with logic 0 is detected. No simulation on faulty circuit is needed. No fault list enumeration is needed.
Test Generation 1. Conventional test generation for stuck-at faults can be modified to detect BFs. 2. No fault propagation. 3. Must make sure the faults result in a conducting path between VDD and GND. Switch level test generation may be necessary. 4. Break and stuck-open faults are difficult to detect.
Test generator for bridging faults Again, assume A1-A6 are satisfied 1. For the bridging fault BF (a, b) to be detected, add an XOR gate with its inputs connected to a and b. 2. The test generator work is simply to set the output of the XOR gate to 1. No Fault propagation.
Current monitoring Techniques CUT BICS Current Supply Monitor DUT ATE External monitoring Test Fixture Built-In Current Sensor
External Devices Problems: 1. Current resolution is limited. 2. Test equipment must be modified. 3. Current cannot be measured at the full speed of the tester. 4. Cannot partition circuit. Transistor conducts in normal mode and is open in test mode
Built-in Current Sensors (BICSs) BICS CUT Test Pass /Fail VDD Inputs Outputs OR CUT BICS Inputs Outputs Test Pass /Fail VDD Sometimes called ISSQ testing
BICS Based on Logic Threshold Normal : t = 1 Test : t = 0 For correct operation No path to VDD from gates of MTD transistors tout = 1 if no fault = 0 if fault exists
Improvement on Favalli's design Pull- up Pull- down Pull- up Pull- down Pull- up Pull- down MT MTD Gnd tout VDD inputs... t Merge all MT and MTD respectively
Using BiCMOS design Pull- up Pull- down Pull- up Pull- down Pull- up Pull- down MT MTD Gnd tout VDD inputs... Improvement on Favalli's Design
BICS Based on Dual Power Supply & Operational Amplifier - + V in =3V Threshold detector Fault indication CUT V DD =3V RSRS V out + V ou t - V DD '=5V V SS I-I- I+I+ Virtual Short IRS I DD Virtual short VDD~V in Infinite input impedance of OP I - =0 and IRS=IDD
BICS Based on Current Conveyor Virtual Short V'DD=5V Iz Ix VDD CUT Current Conveyor Iy Fail/Pass Threshold Detector Virtual short VDD ~ V DD ' Current Conveying Iy ~ Ix
Advantages of Built-In Current Sensors (BICS) Higher test rate compared to external devices Easier to partition circuits Easier to control current resolution Suitable for mixed-mode circuits Built-In self test capability achievable Lower test equipment cost On-Line testing possible
Disadvantages of BICS Impact on circuit performance Reliability of itself Area overhead Power consumption
Company HP Sandia I DDQ Without I DDQ With I DDQ Without I DDQ With I DDQ No Test Only Funct Only Scan Both Functional Tests Reject ratio (%) HP and Sandia Lab Data HP – static CMOS standard cell, 8577 gates, 436 FF Sandia Laboratories – 5000 static RAM tests Reject ratio (%) for various tests:
Failure Distribution in Hewlett-Packard Chip
Sematech Study IBM Graphics controller chip – CMOS ASIC, 166,000 standard cells 0.8μ static CMOS, 0.45μ lines (L eff ), 40 to 50 MHz clock, 3 metal layers, 2 clocks Full boundary scan on chip Tests: Scan flush – 25 ns latch-to-latch delay test 99.7 % scan-based stuck-at faults (slow 400 ns rate) 52 % SAF coverage functional tests (manually created) 90 % transition delay fault coverage tests 96 % pseudo-stuck-at fault coverage I DDQ tests
Sematech Conclusions Hard to find point differentiating good and bad devices for I DDQ & delay tests High # passed functional test, failed all others High # passed all tests, failed I DDQ > 5 mA Large # passed stuck-at and functional tests Failed delay & IDDQ tests Large # failed stuck-at & delay tests Passed I DDQ & functional tests Delay test caught failures in chips at higher temperature burn-in – chips passed at lower temperature
Current Limit Setting Should try to get it < 1 mA Histogram for 32 bit microprocessor
Delta I DDQ Testing (Thibeault) Use derivative of I DDQ at test vector i as current signature ΔI DDQ (i) = I DDQ (i) – I DDQ (i – 1) Leads to a narrower histogram Eliminates variation between chips and between wafers Select decision threshold Δ def to minimize probability of false test decisions
|I DDQ | and | I DDQ |
Setting Threshold I DDQ ΔI DDQ Mean (good chips)0.696 μA-2×10 -4 μA Mean (bad chips)1.096 μA0.4 μA Variance0.039 (μA) (μA) 2 Δ def Error Prob × × ×10 -6
Summary I DDQ test is used as a reliability screen Can be a possible replacement for expensive burn-in test I DDQ test method has difficulties in testing of sub-micron devices Greater leakage currents of MOSFETs Harder to discriminate elevated I DDQ from 100,000 transistor leakage currents ΔI DDQ test may be a better choice Built-in current (BIC) sensors can be useful