1. TinyOS Research Overview
Jason Hill

2. A symphony of embedded devices.
-Wireless Vision
Asset Tracking
Military Scenarios
Security
Home Automation
A symphony of embedded devices.

3. How do they fit together?
The Pieces Exist
Low-power CMOS radios
System-on-chip manufacturing capabilities
Ad-hoc networking protocols
Distributed algorithms
Low-power microcontrollers
How do they fit together?

4. Systems Development Spiral
System Capabilities
Hardware
Software
NEST Services
Dot
Mica
2002
Today
Rene
2001
TinyOS
2000
weC Mote
Communication Stack
Hardware supporting software to enable applications.

5. Design Lineage COTS dust prototypes (Kris Pister et al.)
weC Mote (~30 produced)
Rene Mote (850+ produced)
Dot (1000 produced)
Mica node (current, produced) ?

6. Complete Software Vision
Power
Timing
Leader Election
Network Prog
Sensor Boards
DSP algorithms
Event Detection
Timestamp
Acks
Time Sync.
Secure Communication
Data Presentation
Networking Stack
Application Code
External Control
Localization
Reliable Delivery
Routing
Data Aggregation/Query Processing
Apps
Middleware
Platform

7. Mica Platform Users TEMPLE UNIVERSITY UNIV SOUTHERN CALIFORNIA
UNIVERSITY OF CALIFORNIA
UNIVERSITY OF CINCINNATI
UNIVERSITY OF COLORADO
UNIVERSITY OF ILLINOIS
UNIVERSITY OF IOWA
UNIVERSITY OF KANSAS
UNIVERSITY OF MICHIGAN
UNIVERSITY OF NOTRE DAME
UNIVERSITY OF SOUTHERN CA
UNIVERSITY OF TEXAS
UNIVERSITY OF UTAH
UNIVERSITY OF VIRGINIA
US ARMY CECOM
USC INFORMATION SCIENCES
VANDERBILT UNIVERSITY
VIGILANZ SYSTEMS
VITRONICS INC
WASHINGTON UNIVERSITY
WAYNE STATE UNIVERSITY
WILLOW TECHNOLOGIES LTD
WJM, INC
XEROX
ALLEN, ANTHONY
ALTARUM
BAE SYSTEMS CONTROLS
BALBOA INSTRUMENTS
BUDNICK, LARRY
CARNEGIE MELLON UNIV
CLEVELAND STATE UNIV
CORNELL UNIVERSITY
DARTMOUTH COLLEGE
DOBLE ENGINEERING COMPANY
DUKE UNIVERSITY
FRANCE TELECOM R&D
GE KAYE INSTRUMENTS, INC
GEORGE WASHINGTON UNIV.
GEORGIA TECH RESEARCH INT
GRAVITON, INC
HRL ABORATORIES
INTEL CORPORATION
INTEL RESEARCH
JPL ACCOUNTS PAYABLE
KENT STATE UNIVERSITY
LAWRENCE BERKELEY NAT'L
LLNL
LOS ALAMOS NATIONAL LAB
MARYLAND PROCUREMENT
MIT
MIT*
MITRE CORP.
MSE TECH. APPLICATION INC
NASA LANGLEY RESEARCH CTR
NAT'L INST OF STD & TECH
NICK OLIVAS LOS ALAMOS NA
NORTH DAKOTA STATE UNIV
PENNSYLVANIA STATE UNIV
ROBERT BOSCH CORP.
RUIZ-SANDOVAL, M.E.
RUTGERS STATE UNIVERSITY
SANDIA NATIONAL LABS
SIEMENS BUILDING TECH INC
SILICON SENSING SYSTEMS
SOUTHWEST RESEARCH

8. Nesc – Building software like hardware
Nesc is:
Component based software extension to C
Provides separation of construction and composition
Component behavior described in terms of interfaces
Structure around bidirectional event based interfaces
Static compile-time optimization eliminates overhead

9. Real World Apps…
What have we done with this stuff?

10. Vehicle Tracking

11. Cory Energy Monitoring/Mgmt System
50 nodes on single floor
5 level ad hoc net
30 sec sampling
250K samples to database over 6 weeks

12. Structural performance due to multi-directional ground motions (Glaser & CalTech)
Mote Layout
Mote infrastructure 14 13 5 ` 15 15 6 12 11 9 8
Comparison of Results
Wiring for traditional structural instrumentation
+ truckload of equipment

13. Node Localization

14. Multi-dimensional node tracking
Track unmodified “evader” through a network of magnetic sensors.
In-network processing to estimate planar position of vehicle
Geographic multi-hop networking to route data to automated camera
Camera controlled to track vehicle
Video: demo.mpeg

15. Next-Generation Nodes
Integrated processing, storage, communication and sensing onto a single silicon die
Greatly reduce manufacturing cost
Improve efficiency through incorporation of specialized accelerators

16. General Architecture Diagram

17. General Architecture Single CPU for Base band, OS and Application
Shared system resources can be divided between system components dynamically
High bandwidth, flexible interfaces can be exposed across system components
Allows applications access to fine-grained system control
Hardware accelerators to support key sensor network challenges
Communication, synchronization, power management, concurrency
Shared memory interface model

18. Spec Layout IO Pads RAM blocks MMU logic Debug logic ADC AVR CPU Core
RF Frequency Synthesizer
Transmitter
.25 um CMOS
Core Area only 50% full…

19. Spec Demonstration…