3 Fault Model and Structural Tests Fault model is the foundation of structural testing methodsStructural testsUse the information of interconnected components (e.g., gates) to derived test regardless of the functionsDefine faults fault coverage (quality evaluation) ATPG to generate tests for faults DfT for enhancing fault detection.Why Model Faults?As mentioned before, functional test set which is the functional vectorscreated for design verification may not work well to detect themanufacture faults. The reason is that both tests are targetingdifferent purposes. One is to detect the design errors.Another one is to detect the physical defects.We also mentioned before that the exhaustive testing is prohibitivelyexpensive even for a small circuit.
4 Characteristics of Fault Models Model the effects of physical defects on the logic function and timingIdentifies target faultsModel faults (defects) most likely to occurDepends on the process, design platform, design style, design level, etc.Limits the scope of test generationCreate tests only for the modeled faultsWhy Model Faults?There are some many possible defects or faults which can happenduring the manufacturing process. In each test generation,we should identify some target faults to generate the correspondingtest set. In this way, we also can limit the scope of test generationand make the analysis possible.Especially, we may like to focus on those faults mostly likely to occur.Based on the fault models and the circuits, we can then generatethe test set manually or automatically.The test set can therefore be evaluated by faultsimulations or experiments to reflect its effectiveness.The evaluation can also help in diagnosis on the possible causes ofthe defects in the chips. This can typically be achieved byassociating specific defects with specific test patterns createdbased on some fault models.
6 Defect, Fault, and Error Defect Error Fault Physical imperfection The unintended difference between the implemented hardware and its intended designErrorA wrong output signal produced by a defective systemFaultA representation of a defect at the abstracted function levelOne of the gate input terminal was mistakenly connected to groundDefect: short to groundError: f = 0 when a = b = 1Fault: b stuck at 0afb
7 Common Fault Models Stuck-at faults Interconnect short and opens Transistor stuck-on/open faultsMemory faultsDelay faults
8 Single Stuck-At Fault Model Assumptions:Only One line is faultyFaulty line permanently set to 0 or 1Fault can be at an input or output of a gateOne of the gate input terminal was mistakenly connected to groundFault: b stuck at 0signal b will always be “0”a我們來看一個重要且最常用的錯誤模型，Single stuck-at faults，在此一模型下，我們做了幾個假設：一、電路中，只有一信號線有錯誤二、錯誤的信號線的邏輯值不是0就是1三、錯誤只會出現在邏輯閘的輸入或輸出端fb
9 The Popularity of Single Stuck-At Faults Complexity is greatly reducedTechnology independentCan be applied to TTL, ECL, CMOS, BiCMOS etc.Design style independentGate array, standard cell, custom VLSIDetection capability of un-modeled defectsEmpirically many defects accidentally detected by test derived based on single stuck-at fault
10 Multiple Stuck-At Faults Several stuck-at faults occur at the same timeFor a circuit with k linesthere are 2k single stuck-at faultsthere are 3k-1 multiple stuck-at faultsA line could be stuck-at-0, stuck-at-1, or fault-freeOne out of 3k resulting circuits is fault-freeMost Multiple faults are covered by single-fault tests of combinational circuit:4-bit ALU (Hughes & McCluskey, ITC-84) All double and most triple-faults covered.Large circuits (Jacob & Biswas, ITC-87) Almost 100% multiple faults covered for circuits with 3 or more outputs.Multiple Stuck-At FaultsThe multiple stuck-at fault models assume that there are several stuck-atfaults occurring at the same time. It can reflect the real faulty situationespecially for high density circuits in VLSI designs.Given a circuit with k lines, there are 2k single stuck-at faults,while there are 3 to the power of k minus 1 multiple stuck-at faults.The number of multiple stuck-at faults of any real circuits will beextremely large.
11 Bridging Faults For CMOS Logic Two or more normally distinct points (lines) are shorted togetherCould be AND-bridging or OR-bridgingdepends on the inputsVDDABGNDfCDgbridging(A=B=0) and (C=1, D=0)(f and g) is OR-bridging faultpull to VDDpull to zero(A=B=0) and (C=1, D=1)(f and g) is AND-bridging fault
12 Interconnet OpensOpen defects are due to a defect which splits up a node into two or more distinct nodes.Large open (break): No current can go between the two ends of the open when a voltage is applied across it.Narrow open: The opening is usually < 100 nm. In this case a small leakage current (by tunnel effect) go across the open.VDDCDGNDgVDDAOpen defectsas a large resistorfBAGND
13 CMOS Transistor Stuck-On IDDQ currentVDDExample:N transistoris always ONOutput level?stuck-onTransistor Stuck-OnMay cause ambiguous logic levelDepends on the relative impedances of the pull-up and pull-down networksWhen Input Is Low in the exampleBoth P and N transistors are conducting, causing increased quiescent current, called IDDQ faultGND
14 CMOS Transistor Stuck-Open May cause the output to be floatingThe faulty cell has sequential behaviorStuck-open might require two vector testsVDDstuck-openInitializationvector(0/0) ->(1/0)Faulty value1 -> 0GND
15 Pseudo-Stuck-At Fault Model It is similar to single stuck-at fault model, except that every cell output is considered observable by IDDQ testing.The fault site at a gate input requires sensitization and propagation to an output of the same gate (but not to an output of the device) in order to be given credit for IDDQ fault detection.我們來看一個重要且最常用的錯誤模型，Single stuck-at faults，在此一模型下，我們做了幾個假設：一、電路中，只有一信號線有錯誤二、錯誤的信號線的邏輯值不是0就是1三、錯誤只會出現在邏輯閘的輸入或輸出端a=11/0b=1f=0c=0
17 Memory Faults Parametric Faults Functional Faults 0 0 0 0 d b 0 a 0 SpeedPower ConsumptionNoise MarginData Retention TimeFunctional FaultsStuck Faults in Address Register, Data Register, and Address DecoderCell Stuck FaultsAdjacent Cell Coupling Faultsthe presence of a faulty signal depends on the signal values of the neighboring cellsPattern-Sensitive FaultsPattern sensitivity between cellsMemory FaultsThe testing of memories is not only to detect the functional faults,but also to detect parametric faults.The parametric faults are to model the faulty operationsin terms of the following concerns: output level,power consumption, noise margin and data retention time.There are several kinds of functional faults associated with memory.1. The typical stuck-at faults in address registers, data registers,and address decoders.2. Some cell stuck-at faults3. Adjacent cell coupling faults. This fault happens on the adjacent cellswhen some specific combinations of values on these cells.4. Pattern-sensitive faults. This fault happens on the neighboring cellsThe last two kinds faults are unique to the memory structures andare very different from the other functional faults.0 d b0 a 0a=b=0 => d=0a=b=1 => d=1
18 Delay Fault Models Delay faults change the timing of circuit. Testable when circuit operates at higher speedInsufficient stuck-at testsChip with timing defects may pass the low speed stuck-fault testing, but fail at the system speedTypesTransition Fault, Gate Delay Fault, Line Delay Fault, Path Delay Fault, Segment Delay Fault
19 Fault Model Summary Current practice Single stuck-at faultsTransition faultsOther models to enhance defect coverageN-detect faultsInterconnect open faults and bridging faultsStuck-open (CMOS)Path delay faults (high performance circuits)
21 Definition Of Fault Detection A test (vector) t detects a fault f ifft detects f z(t) ≠zf(t)Note that there can be multiple outputs for z(t)A fault f is said to be detectableIf there exists a test t that detects f; otherwise, f is undetectable.ExampleX1Z1xs-a-1XFault DetectionA test t is said to detect a fault f in a circuit if and only ifWhen we apply the input vector t to the circuit,the output of the circuit is different in the situations offault free and with the fault f.In the example, there is a stuck-at-1 fault appearing at one of the inputof the AND gate. When we apply the test 100, the outputs of fault-freeand faulty circuits are different. So the test 100 detects the fault f.Z1=XX23f2ZX23The test (x1,x2,x3) = (100) detects f because z1(100)=0 while z1f (100)=1
22 Redundancy of FaultsFor combinational circuits, an undetectable fault is corresponding to a redundant wire.Undetectable faults do not change the function of the circuitThe wire can be connected to a constant value without changing circuit’s function.
23 Examples of Simplifying Circuits with Redundancy If l s.a.1 is undetectable, the gate can be simplified asIf l s.a.0 is undetectable, the entire gate can be removed & replaced by a constant 0 wirexmnls. a. 1Y1xmnls. a. 0Y
24 Cause of Circuit Redundancy Design to satisfy certain physical characteristicsSpeed: carry look-ahead addersFault tolerant circuits: triple module redundant (TMR)Un-intentional redundancy by design partitioning.Under specified requirements.
25 Example: Redundancy Removal Redundant faults: e s-a-1, d s-a-0 and d s-a-1The NAND gate with d is redundantaee sa1dcfbDetectabilityA fault f is said to be detectable if there exists a test t that detects f;otherwise, f is an undetectable fault.For an undetectable fault, the fault-free and the faulty values remainthe same under any input vector. In other words, there is not an inputvector which can simultaneously activate f and create a sensitized pathto at least a primary output.simplify the redundantsignals and gatesacfb
26 Fault a is undetectable, i.e., f(t) = fα(t) for all t. Fault MaskingThe existence of an undetectable fault may invalidates the test for another fault.Test pattern masking by undetectable faultsaea e sa1dcfbFault a is undetectable, i.e., f(t) = fα(t) for all t.
27 Fault b can be detected by test vector 1101. (X10X) gb g sa01/00/1In the presence of the undetectabe fault a, the test vector 1101 becomes invalidate for fault b.acbdf1gb g sa01/00/1
28 But fault b can also be detected by test vector 010X with fault a. 1Xgb g sa01/00/1
30 Fault Equivalence Distinguishing test Equivalent Faults A test t distinguishes faults a and b ifEquivalent FaultsTwo faults, a & b are said to be equivalent in a circuit , iff the function under a is equal to the function under b for any input combination (sequence) of the circuit.No test can distinguish between a and bIn other words, test-set(a) = test-set(b)Fault EquivalenceA test t is said to be able to distinguish between fault A and Bif the outputs of the circuit are different under fault A and Fault Bwhen we apply test t.So, two faults A and B are said to be equivalent in a circuit, if and onlyif the function under fault A is equal to the function under fault B forany input combinations of the circuits.In this case, no test can distinguish those two faults so that any testwhich detects one of them detects all of them. The equivalent faultscan thus be grouped together as a class and only one representativefault should be used for the test generation to save the CPU timefor the test generation & fault simulation process.
31 Equivalence Analysis of a Single Gate ABCA sa1B sa1C sa1A sa0B sa0C sa0001011011ACBFault Equivalence Class(A s-a-0, B s-a-0, C s-a-0)Faults that can be ignored:A s-a-0, B s-a-0, or C s-a-0
32 Fault Equivalence of Faults on a Gate AND gate:all s-a-0 faults are equivalentOR gate:all s-a-1 faults are equivalentNAND gate:all the input s-a-0 faults and the output s-a-1 faults are equivalentNOR gate:all input s-a-1 faults and the output s-a-0 faults are equivalentInverter:input s-a-1 and output s-a-0 are equivalent input s-a-0 and output s-a-1 are equivalentxxs-a-0s-a-0same effectFault EquivalenceFor AND gate, all the stuck-at-0 faults of any inputs and the outputare equivalent.For OR gate, all the stuck-at-1 faults of any inputs and the outputFor NAND gate, all the stuck-at-0 faults of any inputs and thestuck-at-1 fault of the output are equivalent.For NOR gate, all the stuck-at-1 faults of any inputs and the outputstuck-at-0 fault are equivalent.For Inverter, the input stuck-at-0 and the output stuck-at-1 faultsare equivalent. The input stuck-at-1 and the output stuck-at-0 faults
33 Equivalence Fault Collapsing of a Single Gate n+2 instead of 2(n+1) faults need to be considered for n-input gatess-a-1s-a-0s-a-1s-a-1s-a-0s-a-0s-a-1s-a-0Equivalent Fault CollapsingCollapsing a equivalence fault class into only one representative faultis called equivalence fault collapsing.For an n-input basic gate, there are totally 2n+2 stuck-at faultsassociated with its inputs and output.After we perform the equivalence fault collapsing, there are only n+2 faultsneeded to be considered as shown in the slide.s-a-1s-a-0s-a-1s-a-1s-a-0s-a-0s-a-1s-a-0
34 Equivalent Fault Group In a combinational circuit, many faults may form an equivalent groupThese equivalent faults can be found by sweeping the circuit from the primary outputs to the primary inputsTransitive Rule: When a == b and b == g, then a == gs-a-0s-a-1xxFault EquivalenceTwo equivalent faults are detected by exactly the same tests.Because they will cause exactly the same faulty circuit behavior.Three faults shown in the slide are equivalent.s-a-1xThree faults shown are equivalent !
35 Finding Equivalent Fault Groups Construct a GraphA node is a faultWhen there is a link between two node, the two faults are equivalenta s-a-0a s-a-0Fault EquivalenceTwo equivalent faults are detected by exactly the same tests.Because they will cause exactly the same faulty circuit behavior.Three faults shown in the slide are equivalent.c s-a-1xxb s-a-0c s-a-1xb s-a-0
36 Example of Finding Equivalent Fault Groups Construct a bigger fault equivalent graph by sweeping the netlist from PO’s to PI’sabdecFault EquivalenceTwo equivalent faults are detected by exactly the same tests.Because they will cause exactly the same faulty circuit behavior.Three faults shown in the slide are equivalent.b s-a-0a s-a-0d s-a-1c s-a-1e s-a-1
37 Limitation of Structural Analysis b s-a-0f s-a-1dThere is no rule to guarantee equivalence between faults of branches.It is a special case here b s.a.0 == f s.a.1In general, they cannot be identified by simple structure analysis.
38 Fault Dominance Dominance Relation A fault b is said to dominate another fault a in an irredundant circuit, iff every test (sequence) for a is also a test (sequence) for b.I.e., test-set(b) > test-set(a)No need to consider fault b for fault detection once a is detectedFault DominanceA fault B is said to dominate another fault A in an irredundant circuit,if and only if every test (sequence) for A is also a test (sequence) for B.In this case, there is no need to consider fault B for fault detectionas long as the fault A is considered.is dominated by bTest(b)Test(a)
39 Fault Dominance AND gate: NAND gate: OR gate: NOR gate: Output s-a-1 dominates any input s-a-1NAND gate:Output s-a-0 dominates any input s-a-1OR gate:Output s-a-0 dominates any input s-a-0NOR gate:Output s-a-1 dominates any input s-a-0Dominance fault collapsing:The reduction of the set of faults to be analyzed based on dominance relationEasier-to-testxxs-a-1s-a-1harder-to-testFault DominanceThe reduction of the set of faults to be analyzed based on the dominancerelation is called dominance fault collapsing.For an AND gate, the output stuck-at-1 fault dominates any input stuck-at-1faults.For an NAND gate, the output stuck-at-0 fault dominates any input stuck-at-1For an OR gate, the output stuck-at-0 fault dominates any input stuck-at-0For an NOR gate, the output stuck-at-1 fault dominates any input stuck-at-0
40 Dominance Analysis of a Single Gate ABCA sa1B sa1C sa1A sa0B sa0C sa0001011011ACBFault Dominance Relations(C s-a-1 > A s-a-1) and (C s-a-1 > B s-a-1)Faults that can be ignored for test generation:C s-a-1
41 Complete Fault Collapsing of a Single Gate Equivalence + DominanceFor each n-input gate, we only need to consider n+1 faults during test generations-a-1s-a-0s-a-1s-a-0s-a-1s-a-0Equivalent Fault CollapsingCollapsing a equivalence fault class into only one representative faultis called equivalence fault collapsing.For an n-input basic gate, there are totally 2n+2 stuck-at faultsassociated with its inputs and output.After we perform the equivalence fault collapsing, there are only n+2 faultsneeded to be considered as shown in the slide.s-a-1s-a-0s-a-1s-a-0s-a-1s-a-0
42 Dominance Analysis for a Group of Faults Construct a dominance graphA node is a faultWhen fault a dominates fault b, then an arrow is pointing from a to ba s-a-1a s-a-1c s-a-0xxb s-a-1c s-a-0xb s-a-1
43 Example of Finding Dominant Fault Groups Construct a bigger fault equivalent graph by sweeping the netlist from PO’s to PI’sabdeca s-a-1c s-a-0Fault EquivalenceTwo equivalent faults are detected by exactly the same tests.Because they will cause exactly the same faulty circuit behavior.Three faults shown in the slide are equivalent.b s-a-1d s-a-0e s-a-0
44 Fault Collapsing Flow Equivalence Start Sweeping the netlist from PO to PITo find the equivalent fault groupsEquivalenceanalysisSweeping the netlistTo construct the dominance graphDominanceanalysisDiscard the dominating faultsSelect a representative fault fromeach remaining equivalence groupGenerate collapsed fault listDone
45 Checkpoint Theorem Checkpoints Theorem Checkpoints = primary inputs + fanout branchesIn a combinational circuit, any test which detects all single stuck faults on all checkpoints detects all single faults in the circuit.Checkpoint TheoremBecause the fault collapsing based on the prime faults is difficult to do.There is a simple approach called the Checking Theorem which can providesa fairly good reduction in the test set.In a irredundant combinational circuit, the set ofcheckpoints consists of the primary inputs and all thefanout branches. In a fanout-free circuit,the set of checkpoints consists of the primary inputs alone.The Theorem says that any test set which detects all single (multiple)stuck-at faults on check points will detect all single (multiple)stuck faults.The faults marked by X are checkpoint faults.
46 Why Inputs + Branches Are Enough ? Sweeping the circuit from PO to PI to examine every gate and replace output faults by input faults until a PI or branch is met.Based on an reversed levelized order: EDABCIf a branch is met, start the above process from the stem again.In this example, checkpoints are marked in solid blue.APO branch faults are ignored, since they are represented by gate output faults, e.g., D’s outputDBEC
47 An Example of Fault Collapsing + Checkpoint 10 checkpoint faultsa s-a-0 == d s-a-0, c s-a-0 == e s-a-0 b s-a-0 > d s-a-0, b s-a-1 > d s-a-1Note that the branch dominance is not obvious.6 out of 10 faults are enough.aFault CollapsingThe set of checkpoint faults can be further reduced by using the equivalenceand dominance relations.In the example, there are 10 checkpoint faults.After the equivalence and dominance checking, 6 tests are enough for thecomplete coverage of all faults.dfhbgec