Presentation on theme: "RTL design in python: porting the mMIPS"— Presentation transcript:
1RTL design in python: porting the mMIPS Jos HuiskenJune 25th, 2013Title: RTL design in python: porting the mMIPS.Abstract: Can you do RTL design in a general purpose programming language? Yes, you can very conveniently with Python using an open-source package named MyHDL. In this presentation I will introduce MyHDL and share the experience in porting the mMIPS from SystemC.After introducing the basic MyHDL modelling techniques, where Python generators are used to model hardware concurrency, we'll address shortly (co-)simulation and the connection with Xilinx and Cadence design environments using the mMIPS. The real convenience however of enabling RTL design in a general purpose programming language is in high level modelling and verification. For instance verification against Matlab style specifications can be performed within a single program.
3What is Python? A general purpose programming language Growing in popularityInterpreted language (bytecode-interpretive)Multi-paradigmClean object-orientedFunctional – in the LISP traditionStructural (procedural-imperative)Extremely readable syntaxVery high-levelListsDictionaries (associative arrays)Extensive documentation
4What is MyHDL? A Python package which enables hardware description Open-source projectBatteries included (more on this later)
5MyHDL Extends Python MyHDL is Python Using Python constructs to extend Object OrientedSignal, intbvGeneratorsMicro-thread like, enables concurrency behaviorResumable functions that maintain stateDecoratorsMeta-programming“Macro” mechanismModifies a function / generator@always_seq
6Why use MyHDL Manage Complex Designs New to Digital Hardware Design Scripting Languages Intensively UsedModern Software Development Techniques for Hardware DesignAlgorithm Development and HDL Design in a Single EnvironmentRequire Both Verilog and VHDLVHDL Too VerboseSystemVerilog Too ComplicatedYou Been TCL’d too much
7What MyHDL is NOT Not arbitrary Python to silicon Not a radically new approachNot a synthesis toolNot an IP block libraryNot only for implementationNot well suited for accurate time simulation
9Register Transfer Register Transfer Level (RTL) abstraction This is the commonly excepted description of mainstream HDLs: Verilog and VHDLDescribes the operations between registersMyHDL operates at the Register Transfer Level (RTL)MyHDL extends Python for hardware description
10MyHDL Types intbv Signal Convertible types Bit vector type, an integer with bit vector propertiesSignalDeterministic communication, see it as a VHDL signalConvertible typesboolinttuple of intlist of bool and list of intbv
11MyHDL Generators A Python generator is a resumable function Generators are the core of MyHDLProvide the similar functionality as a VHDL process or Verilog always blockyield in a generator
12Python generator: Fibonacci # function versiondef fibon(n):a = b = 1result = for i in xrange(n):result.append(a)a, b = b, a + breturn resultfibon(8)[1, 1, 2, 3, 5, 8, 13, 21]# generator versiondef fibon(n):a = b = 1result = for i in xrange(n):yield aa, b = b, a + bfor x in fibon(8):print x,
13MyHDL Decorators MyHDL Decorators “creates ready-to-simulate generators from local function definitions”@instance@always(sensitivity list)@always_seq(clock,reset)@always_comb
14Python decorator@mydecoratordef myfunc():return# is equivalent tomyfunc = mydecorator(myfunc)def verbose(origfunc):# make new funcdef newfunc(*args, **kwargs):print “entering”, origfunc.__name__origfunc(*args, **kwargs)print “exiting”, origfunc.__name__return newfunc@verbosedef myfunc(s):print smyfunc(‘hoi’)entering myfunchoiexiting myfuncA decorator is a function (mydecorator) that takes a function object as an argument, and returns a function object as a return value.@mydecorator: just syntactic sugar
26IIR Type I Digital Filter 1 def m_iir_type1(clock,reset,x,y,ts,B=None,A=None): 2 # make sure B and A are ints and make it a ROM (tuple of ints) 3 b0,b1,b2 = map(int,B) 4 a0,a1,a2 = map(int,A) 5 6 ffd = [Signal(intbv(0, min=x.min, max=x.max)) for ii in (0,0)] 7 fbd = [Signal(intbv(0, min=x.min, max=x.max)) for ii in (0,0)] 8 # intermidiate result, resize from here 9 ysop = Signal(intbv(0, min=dmin, max=dmax)) 10 reset=reset) 12 def hdl(): 13 if ts: 14 ffd.next = ffd 15 ffd.next = x fbd.next = fbd 18 fbd.next = ysop//Am # truncate (>>) # extra pipeline on the output at clock 21 ysop.next = (b0*x) + (b1*ffd) + (b2*ffd) - \ 22 (a1*fbd) - (a2*fbd) # truncate to the output word format 25 y.next = ysop//Am # truncate (>>) return hdl
28Test Frameworks Test frameworks are easy Enables new levels or reuse Test Driven Design (TDD)Existing test environmentspy.testnoseunittest
29Example: fpgalink Test code Application code Host interface software Connect the host software to the DUTHost driver + USB controllerFPGA logic (HDL)External models and checkersPhysical transducershttps://github.com/cfelton/minnesota
30Conclusion Python MyHDL mMIPS Easy to learnBatteries includedMyHDLHardware description in PythonPowerful environment, ecosystemVerification simplified and funmMIPSPorted from SystemCSimulated and Co-Simulated, not fully verifiedSynthesized: ISE (untested) and Cadence rc (co-simulated)Python: allows (…) matlab style interaction
31Short MyHDL History Jan Decaluwe Creator of MyHDLFounder & Board Member EasicCreated MyHDL betweenFirst Release on SourceForge Sep 30, 2003MyHDL ASIC
32Acknowledgement You guys Christopher Felton for hosting and providing the mMipsChristopher FeltonSeveral slides came from him!
33Resources ?? Any Further Questions ?? http://www.myhdl.org And an invitation to join (still) password protected:?? Any Further Questions ??