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Real- time Dynamic Voltage Scaling for Low- Power Embedded Operating Systems Written by P. Pillai and K.G. Shin Presented by Gaurav Saxena CSE 666 – Real Time Systems

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Introduction Energy consumption is an important issue in embedded systems Mobile and portable device Laptops, PDA’s Cellular phones, camcorders Real Time Dynamic Voltage Scaling (RT-DVS) Reduces Energy consumption by lowering the supply voltage and operating frequency. Modify OS’s real-time scheduler and task management service to maintain real-time deadline

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Facts High performance is needed for a small fraction of time, while for the rest of time, a low performance, a low power processor would suffice Low performance is achieved by lowering the operating frequency of the processor when full speed is not needed. Processors are based on CMOS Logic - has voltage dependent maximum operating frequency– V α f ( so at lower frequency, the processor can operate at lower voltage) Energy dissipated per cycle E α V 2 (Higher the frequency level, higher the energy consumption)

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RT-DVS Algorithms Static Voltage Scaling EDF Cycle conserving RT- DVS Look Ahead RT - DVS

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Static Voltage Scaling EDF: Motivation wc1wc2 wc3 wc4 Holes in the pre-run schedule imply: EDF Test: ∑(wc i /p i ) < 1 at frequency = F max In other words, whenever ∑(wc i /p i ) < 1 there are holes in the EDF schedule Next arrival of T1 WCi = worst case computation Fmax

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Static Voltage Scaling EDF: exploiting holes wc1 wc2wc3wc4 Next arrival of T1 Pre-run schedule with holes WC i = worst case computation F max Processor typically idles during holes. Instead, the holes can be exploited to slowdown the processor to save energy

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Static Voltage Scaling EDF wc1 wc2wc3wc4 K*wc1K *wc2K * wc3K * wc4 EDF Test: ∑(wc i /p i ) < 1 at maximum frequency = F max Static-VS EDF Test: K* [∑(wc i /p i )] = 1 at frequency = F max /K Next arrival of T1

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Static EDF: example Available frequencies: 1.00, 0.75 D T1 : 16 D T2 : 10 D T3 : 14 D T1 : 24 D T2 : 20 D T3 : 28 D T1 : 16 D T2 : 20 D T3 : 28 D T1 : 16 D T2 : 20 D T3 :

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What if (C i < WC i )?? K*c1K *c2K * c3K * c4 Next arrival of T1 More holes left unexploited Actual computatio n time

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What if (C i < WC i )?? K*c1K *wc2K * wc3K * wc4 Next arrival of T1 Actual computatio n time Task T1 completes Slow down all these tasks proportionally Hole of size = (wc1 – c1)

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What if (C i < WC i )?? (contd..) K*c1 K’ *wc2K’ * wc3K’ * wc4 Next arrival of T1 CPU Cycles are conserved by slowing down the remaining tasks

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Cycle Conserving RT-DVS When a task set completes its first release, compare real execution time with worst case specified initially. Any idle time in that period can be used to conserve energy Rescale frequency that avoid idle cycles, surplus time is used to run other remaining tasks at lower frequency

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Cycle conserving EDF: Example Task (Fmax): T1 = (3,6) and T2 = (6,12) U = 3/6 + 6/12 = (Fmax) T1 013 Frequency FmFm Time T2 10 New utilization = 1/6 + 6/12 = 0.67 Finding the right “k” (1*k)/6 + (6*k)/12 = 1 K = (1/0.67) New freq = (0.67) Fmax

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DVS-RT Problem Definition N Tasks each caracterized by: A fixed period P i A deadline D i Worst-case Execution Time (WCET) C i Actual Execution Time AC i Objective: Find the best task scheduling and clock frequency in order to: Minimizing energy consumption. Meeting all the deadlines.

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Task set: Task Worst case computation time Period/ Deadline Invocation 1 (ac1) Invocation 2 (ac2) 13ms 8ms2ms1ms 23ms10ms1ms 3 14ms1ms At freq. : f m

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Look-Ahead EDF Defer as much works as possible and set initially to the minimum possible frequency. Hence at later stage if a task uses much less than it worst case, deferred work may never be needed. It ensures that there are sufficient cycles available for each task to meet its deadline after reserving cycles for higher priority jobs. Best saving of energy.

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(a)Plan to defer T3’s execution time until after D1 but, by D3 Look-ahead EDF step 1 of ms D freq. T3 D2D3 Reservation for T1 Reservation for T2

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(b) Find u so as to finish T1 by D1 and T2 by D2 Look-ahead EDF step 2 of ms T2 D freq. T3 D2D3 Reservation for T1 Reservation for T2T1 T2

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(c) u = 0.75, T1 finishes earlier, find new u for T2 to finish by D2 Look-ahead EDF step 3 of ms T2 D freq. T3 D2D3 Reservation for T1 Reservation for T2 T1 T2 t = 2.67

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Look-ahead EDF step 4 of ms D freq. T3 D2D3 Reservation for T1 Reservation for T2 T1 t = 4.67 T2 (d) α = 0.5, T2 finishes earlier, enough time until D1, but EDF is work conserving, launch T3 at u = 0.5

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Look-ahead EDF step 5 of ms freq.D2D3 T1 t = 8.00 Reservation for T2 T1 T2T3 (e) Guess for T1 again,

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Look-ahead EDF step 6 of ms freq.D2D3 T1 t = 8.00 T1T2T3T2T3 (f) u= 0. 5, every task is dynamically scheduled successfully

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Relative performance schemes Energy savings Look Ahead EDF Cycle Conserving EDF Static Voltage Scaling EDF

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Implementation Scheduler hooking in the kernel

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References and Credits Real time dynamic voltage scaling for low power embedded operating systems, P. Pillai and K.G. Shin, in ACM SOSP, pages , Dynamic Voltage Scaling Algorithms for Hard Real Time Systems, Andrea Romei, Università di Pisa RT- DVS Algorithms by Sungwuk Jung Energy aware real time systems by G. Sudha Anil Kumar, Iowa State University

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