The operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine instruction per cycle. Each instruction cycle can be subdivided into small units. One comprises fetch, indirect, execute and interrupt, with only the fetch and execute cycle always occurring. These smaller cycles involves a series of steps referred to as Micro-operations because each step is simple and does very little.
An instruction cycle' (also called fetch-and-execute cycle, fetch- decode-execute cycle, and FDX) is the time period during which a computer processes a machine language instruction from its memory or the sequence of actions that the central processing unit (CPU) performs to execute each machine code instruction in a program. The name fetch-and-execute cycle is commonly used. The instruction must be fetched from main memory, and then executed by the CPU. This is fundamentally how a computer operates, with its CPU reading and executing a series of instructions written in its machine language. From this arise all functions of a computer familiar from the user's end.
Memory Address Register (MAR) - Connected to address bus - Specifies address for read or write operation Memory Buffer Register (MBR) - Connected to data bus - Holds data to write or last data read Program Counter (PC) - Holds address of next instruction to be fetched Instruction Register (IR) - Holds last instruction fetched
Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches
t1:MAR <- (PC) t2:MBR <- (memory) PC <- (PC) +1 t3:IR <- (MBR) (tx = time unit/clock cycle) or t1:MAR <- (PC) t2:MBR <- (memory) t3:PC <- (PC) +1 IR <- (MBR)
Proper sequence must be followed - MAR <- (PC) must precede MBR <- (memory) because the memory read operation makes use of the address in the MAR Conflicts must be avoided - Must not read & write same register at same time - MBR <- (memory) & IR <- (MBR) must not be in same cycle Also: PC <- (PC) +1 involves addition - Use ALU - May need additional micro-operations
Once the instruction is fetched, the next step is to fetch source operands. If the instruction specifies an indirect address, then an indirect cycle must precede the execute cycle. MAR <- (IR address ) - address field of IR MBR <- (memory) IR address <- (MBR address ) The address field of the instruction is transferred to the MAR. This is then used to fetch the address of the operand. Finally, the address field of the IR is updated from the MBR, so that it now contains a direct rather than an indirect adddress.
After the completion of the execute cycle, a test is made to determine whether any enabled interrupts have occurred. If so, the interrupt cycle occurs. t1:MBR <-(PC) t2:MAR <- save-address PC <- routine-address t3:memory <- (MBR) The contents of the PC are transferred to the MBR, so that they can be saved for return from the interrupt. Then the MAR is loaded with the address at which the contents of the PC are to be saved and the PC is loaded with the address of the start of the interrupt-processing routine. Once this is done, the final step is to store the MBR, which contains the old value of the PC, into memory.
The fetch, indirect and interrupt cycles are simple and predictable. However, due to the variety of opcodes, there are a number of different sequences of micro-operations that can occur during an execution cycle. e.g. ADD R1,X - add the contents of location X to Register 1, result in R1 t1:MAR <- (IR address ) t2:MBR <- (memory) t3:R1 <- R1 + (MBR) The address portion of the IR is loaded into the MAR. Then the referenced memory location is read. Finally, the contents of R1 and MBR are added by the ALU.
ISZ X - increment and skip if zero t1:MAR <- (IR address ) t2:MBR <- (memory) t3:MBR <- (MBR) + 1 t4:memory <- (MBR) if (MBR) = 0 then PC <- (PC) + 1 The new feature introduced here is the conditional action. The PC is incremented if (MBR) = 0. This
BSA X - Branch and save address t1:MAR <- (IR address ) MBR <- (PC) t2:PC <- (IR address ) memory <- (MBR) t3:PC <- (PC) + 1 The address of the instruction that follows the BSA instruction is saved in location X and execution continues at location X+ 1. The saved address will later be used for return. The address in the PC at the start of the instruction is the address of the next instruction in sequence. This is saved at the address designated in the IR. The latter address is also incremented to provide the address of the instruction for the next instruction cycle.
Each phase decomposed into sequence of elementary micro-operations E.g. fetch, indirect, and interrupt cycles Execute cycle - One sequence of micro-operations for each opcode Need to tie sequences together Assume new 2-bit register - Instruction cycle code (ICC) designates which part of cycle processor is in 00: Fetch 01: Indirect 10: Execute 11: Interrupt
1. What are the subdivisions of the Instruction Cycle? Ans: Fetch, Indirect, Execute and Interrupt. 2. Which two subdivisions always occur? Ans: Fetch and Execute. 3. What are micro-operations? Ans: A series of steps performed by each sub-cycle of the instruction cycle.
CONTROL UNIT OPERATION CONTROL UNIT INSTRUCTION REGISTER CONTROL BUS CONTROL SIGNALS FROM CONTROL BUS CLOCK CONTROL SIGNALS TO CONTROL BUS CONTROL SIGNALS WITHIN CPU FLAGS......
CONTROL UNIT OPERATION CONTROL UNIT INPUTS INSTRUCTION REGISTER CLOCK CONTROL BUS SIGNALS FLAGS EACH INDIVIDUAL BIT TYPICALLY HAS SOME MEANING (E.G., OVERFLOW) DECODER (TAKES AN ENCODED INPUT AND PRODUCES A SINGLE OUTPUT COUNTER AS INPUT TO THE CONTROL UNIT
CONTROL UNIT OPERATION CONTROL UNIT LOGIC FOR EACH CONTROL SIGNAL TO DERIVE A BOOLEAN EXPRSSION OF THAT SIGNAL AS A FUNCTION OF THE INPUTS, THAT DEFINE THE BEHAVIOR OF THE CONTROL UNIT AND HENCE OF THE PROCESSOR
CONTROL UNIT OPERATION SINGLE CONTROL SIGNAL NEW CONTROL SIGNALS, P & Q C5 PQ=00 FETCH CYCLE PQ=01 INDIRECT CYCLE PQ=10 EXECUTE CYCLE PQ=11 INTERRUPT CYCLE THE CONTROL SIGNAL C5 WILL BE ASSERTED DURING THE SECOND TIME UNIT OF BOTH THE FETCH AND INDIRECT CYCLES