2Combinational Circuits A combinational logic circuit has:A set of m Boolean inputs,A set of n Boolean outputs, andn switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input valuesA block diagram:m Boolean Inputsn Boolean OutputsCombinatorialLogicCircuit
3Design Procedure Specification Formulation Optimization Write a specification for the circuit if one is not already availableFormulationDerive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specificationApply hierarchical design if appropriateOptimizationApply 2-level and multiple-level optimizationDraw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters
4Design Procedure Technology Mapping Verification Map the logic diagram or netlist to the implementation technology selectedVerificationVerify the correctness of the final design manually or using simulation
5Design Example Specification BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3 code for the decimal digitsBCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectivelyExcess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code wordImplementation:multiple-level circuitNAND gates (including inverters)
6Design Example (continued) FormulationConversion of 4-bit codes can be most easily formulated by a truth tableVariables - BCD: A,B,C,DVariables - Excess-3 W,X,Y,ZDon’t Cares - BCD to 1111
7Design Example (continued) Optimization2-level using K-mapsW = A + BC + BDX = C + D + BY = CD +Z =BCDA132457612131514891110XwzyxBBCDCDD
8Design Example (continued) Optimization (continued)Multiple-level using transformations W = A + BC + BD X = C + D + B Y = CD + Z = G = = 23Perform extraction, finding factor:T1 = C + D W = A + BT1 X = T1 + B Y = CD + Z = G = = 19BCDBCDCDD
9Design Example (continued) Optimization (continued)Multiple-level using transformations T1 = C + D W = A + BT1 X = T1 + B Y = CD + Z = G = 19An additional extraction not shown in the text since it uses a Boolean transformation: ( = C + D = ):W = A + BT1 X = T1 + B Y = CD + Z = G = = 16!BCDCDT1BT1D
10Design Example (continued) Technology MappingMapping with a library containing inverters and 2-input NAND, 2-input NOR, and 2-2 AOI gatesABCDWXYZ
11Beginning Hierarchical Design To control the complexity of the function mapping inputs to outputs:Decompose the function into smaller pieces called blocksDecompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enoughAny block not decomposed is called a primitive blockThe collection of all blocks including the decomposed ones is a hierarchyExample: 9-input parity tree (see next slide)Top Level: 9 inputs, one output2nd Level: Four 3-bit odd parity trees in two levels3rd Level: Two 2-bit exclusive-OR functionsPrimitives: Four 2-input NAND gatesDesign requires 4 X 2 X 4 = 32 2-input NAND gates
12Hierarchy for Parity Tree Example X1X29-InputX3oddZX4OfunctionX5XX6A3-InputX7XAoddB811Ofunction(a) Symbol for circuitXA22XAA33-Input3-InputX4Aodd1BAoddO1BZfunctionfunctionOOXAA522XA63-InputXAodd71BOfunctionXA82(b) Circuit as interconnected 3-input oddfunction blocksAAB1OA2(c) 3-input odd function circuit asinterconnected exclusive-ORblocks(d) Exclusive-OR block as interconnectedNANDs
13Reusable FunctionsWhenever possible, we try to decompose a complex design into common, reusable function blocksThese blocks areverified and well-documentedplaced in libraries for future use
14Top-Down versus Bottom-Up A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinementA bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocksDesign usually proceeds top-down to known building blocks ranging from complete CPUs to primitive logic gates or electronic components.Much of the material in this chapter is devoted to learning about combinational blocks used in top-down design.
15Technology Mapping Mapping Procedures To NAND gates To NOR gates Mapping to multiple types of logic blocks in covered in the reading supplement: Advanced Technology Mapping.
16Mapping to NAND gates Assumptions: The mapping is accomplished by: Gate loading and delay are ignoredCell library contains an inverter and n-input NAND gates, n = 2, 3, …An AND, OR, inverter schematic for the circuit is availableThe mapping is accomplished by:Replacing AND and OR symbols,Pushing inverters through circuit fan-out points, andCanceling inverter pairs
17NAND Mapping Algorithm Replace ANDs and ORs:Repeat the following pair of actions until there is at most one inverter between :A circuit input or driving NAND gate output, andThe attached NAND gate inputs.
19Mapping to NOR gates Assumptions: The mapping is accomplished by: Gate loading and delay are ignoredCell library contains an inverter and n-input NOR gates, n = 2, 3, …An AND, OR, inverter schematic for the circuit is availableThe mapping is accomplished by:Replacing AND and OR symbols,Pushing inverters through circuit fan-out points, andCanceling inverter pairs
20NOR Mapping Algorithm Replace ANDs and ORs: Repeat the following pair of actions until there is at most one inverter between :A circuit input or driving NAND gate output, andThe attached NAND gate inputs.
21NOR Mapping Example A A B B 2 X 1 F C C F 3 D D E E (a) (b) B C F D E
22VerificationVerification - show that the final circuit designed implements the original specificationSimple specifications are:truth tablesBoolean equationsHDL codeIf the above result from formulation and are not the original specification, it is critical that the formulation process be flawless for the verification to be valid!
23Basic Verification Methods Manual Logic AnalysisFind the truth table or Boolean equations for the final circuitCompare the final circuit truth table with the specified truth table, orShow that the Boolean equations for the final circuit are equal to the specified Boolean equationsSimulationSimulate the final circuit (or its netlist, possibly written as an HDL) and the specified truth table, equations, or HDL description using test input values that fully validate correctness.The obvious test for a combinational circuit is application of all possible “care” input combinations from the specification
24Verification Example: Simulation Simulation procedure:Use a schematic editor or text editor to enter a gate level representation of the final circuitUse a waveform editor or text editor to enter a test consisting of a sequence of input combinations to be applied to the circuitThis test should guarantee the correctness of the circuit if the simulated responses to it are correctShort of applying all possible “care” input combinations, generation of such a test can be difficult
25Verification Example: Simulation Enter BCD-to-Excess-3 Code Converter Circuit SchematicAOI symbol not available
26Verification Example: Simulation Enter waveform that applies all possible input combinations:Are all BCD input combinations present? (Low is a 0 and high is a one)Yes, 0000 through 1001 are present.
27Verification Example: Simulation Run the simulation of the circuit for 120 nsDo the simulation output combinations match the original truth table?Yes, the output combinations 0011 through 1100 occur in response to 0000 through 1001, respectively.
28Functions and Functional Blocks The functions considered are those found to be very useful in designCorresponding to each of the functions is a combinational circuit implementation called a functional block.In the past, functional blocks were packaged as small-scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits.Today, they are often simply implemented within a very-large-scale-integrated (VLSI) circuit.
29Rudimentary Logic Functions Functions of a single variable XCan be used on the inputs to functional blocks to implement other than the block’s intended functionTABLE 4-1Functions ofOneVariableXF= 0F= XF=XF = 111111
30Multiple-bit Rudimentary Functions Multi-bit Examples:A wide line is used to represent a bus which is a vector signalIn (b) of the example, F = (F3, F2, F1, F0) is a bus.The bus can be split into individual bits as shown in (b)Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.AFA3231F1242:1F(2:1)24FFF11(c)AFA(a)(b)33,1:04F(3), F(1:0)F(d)
31Enabling FunctionEnabling permits an input signal to pass through to an outputDisabling blocks an input signal from passing through to an output, replacing it with a fixed valueThe value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1When disabled, 0 outputWhen disabled, 1 outputSee Enabling App in text
323-7 Decoding A n-bit binary code can represent up to m=2n elements: m elements n-bit binary codeDecoding - the conversion of an n-bit input code to an m-bit output code with n ≤ m ≤ 2n such that each valid code word produces a unique output codeencoding(ex. 256 alpha-num. chars)(ex. 8-bit ASCII code)decodingA0:An-1D0D1Dm-1n-2ndecodern bitsm-elements≤ 2n
33Decoder examples BCD to 7-segment decoder: Binary to ASCII. Address decoder in a memory:RowDecoder1NaddressExample: 4Mbit DRAMNo. of memory positions: 222This requires 22 address bits:N row address bits (ex. 11)M column addr bit (ex. 11)The address bits are decoded into actual memory locationsMATRIX OFMEMORYCELLS12NMone cellD0=A1’A0’D1=A1’A0D2=A1A0’D3-A1A0ReadWriteControlOut InDataColumn decoder1MColumn addressA1D23
342-to-4 line decoder Table: D0 A0 D1 D2 A1 D3 Logic expressions: D23D0D1D2D3123A0A112-4 lineDecoder?11111Logic expressions:D=A123only one of the inputs is activeD0=A1’A0’D1=A1’A0D2=A1A0’D3-A1A0mintermsA1D23
352-to-4 Line Decoder circuit =A123Notice that the outputs of the decoder correspond to the minterms: Di=mi
36Decoder ExpansionLarger decoders can be realized by implementing each minterm using a single AND gate:However for large decoders this requires multiple input AND gates which is not always feasible.Better to use a hierarchical approach: build larger ones from smaller decoders.Approach:Output AND gates have only 2 inputs and implement the minterms.The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.
37Decoder Expansion - Example 1 3-to-8-line decoderNumber of output ANDs = 8Number of inputs: 33-to-8 decoderA0A12-4DecoderA1’A0A1A0A’1A’0A2’A1’A0’A2’A1’A0A2A1A0A2A1’A0’A2’A1A0’A2’A1A0A’1A0A0A1D0D1D2D32-4DecoderA’1A’0A’1A0AA0’A1A0A2A’21-to-2decoder
39Rule for building large decoders k-to-2k decoder:One needs 2k output AND gatesIf k can be divided by 2:use two k/2-to-2k/2 decodersIf k cannot divided by 2:use a (k+1)/2 anduse a (k-1)/2 decoder.Previous example: 3-to-8 decoder (k=3):Use a 2-to-4 and a 1-to-2 decoder
40Example : build a 4-to-16 decoder How many 2-input output AND gates?Which smaller decoders to use?Draw the circuit.16 output AND gatesK=4 thus k/2=2: one can use two 2-to-4 decoders
414-to-16 decoder Use two 2-to-22 decoders D0 D1 D2 D3 A0 D4 A1 : A2 A3 A3’A2’A1’A0’A3’A2’A1’A0A3A2A1A0A3’A2’A1A0A3’A2A1’A0’A3A2A1A0’D0D1D2D3D4:A0A1D0D1D2D32-4DecoderA1’A0’A1’A0A1A0’A1A0A2A3D0D1D2D32-4DecoderA3’A2’A3’A2A3A2D14D15
42Decoder Expansion - Exercise 2 5-to-32-line decoderNumber of output ANDs = ?Number of inputs to decoders driving output ANDs = ?Which decoders to use to drive the output ANDs?Block diagram:Output NANDs: 32Inputs: 5Which decoders to use to drive the NAND gates: 3-to-8 and a 2-to-4 decoder
44Decoder Expansion - Example 2 7-to-128-line decoderNumber of output ANDs = ?Number of inputs to decoders driving output ANDs = ?Closest possible split to equalNumber of output ANDs = 128Number of inputs to decoders driving output ANDs = 7Closest possible split to equal4-to-16-line decoder3-to-8-line decoder
45Decoder with Enable Extra input EN: See truth table below for function If EN = 1: act as a regular decoderIf EN=0, all outputs are 0See truth table below for functionA0A1D0D1D2D32-4DecoderEN1
46Decoder with Enable: circuit Extra setof andsRegular decoderA0A1D0D1D2D32-4DecoderEN1If one considers EN an input, in that case the circuit can be viewed as distributing value of signal EN(=IN) to 1 of 4 outputs: called a demultiplexer:EN=INA1 A0D0D1D2D3Demux1 0123
47Example: Sprinkler System Design the sprinkler valve controllerDescription:The system has 8 different zonesOnly one value is on at one time (to maintain the pressure)A microcontroller is used to control the valves:However the processor has only 4 outputsLets program the microcontroller to indicate which of the 8 valves should be opened, using a binary representation.From Text by F. Vahid, page 71.
48Sprinkler SystemWe can use a 3-to-8 decoder with enable input controlled by the microprocessorD0=A2’A1’A0’.END1=A2’A1’A0.END7=A2A1A0.ENA0A1A2Micro-controllerabcdEND0D1D2D3D73-8Decoder12When EN=0, all valves are off
49Combinational Logic Implementation - Decoder and OR Gates Implement m functions of n variables with:Sum-of-minterms expressionsOne n-to-2n-line decoderm OR gates, one for each output
50ExampleDesign and implement a majority function F(ABC) using a 3-to-8 decoderTruth table:Minterms:F=m(3,5,6,7)Implementation using decoder:A B C FIndicate MSB, LSB1234567ABC21Fm(3,5,6,7)Thus use a 3-to-8 decoder with OR gate
51Exercise Implement the functions using a 3-to-8 decoder: F2(ABC)=m (0,2,3,5,6,7)F3=AB’ + BCF4(ABC)= A + B + C’For F2: implement F2’=m(1,4): OR and INV= NOR gate with as inputs m1 and m4F3= AB’+BC = AB’(C+C’)+BC (A+A’) = m5 + m4 + m7 + m3F4=A+B+C’: now F4’=A’B’C=m1 Thus F4=m1’ (otherwise F4=m0+m2+m3+m4+m5+m6+m7)
52Answer For F2(ABC)=m (0,2,3,5,6,7) implement F2’=m(1,4): OR and INV= NOR gate with m1 and m4 as inputs.F3= AB’+BC = AB’(C+C’)+BC (A+A’)= m5 + m4 + m7 + m3F4=A+B+C’:now F4’=A’B’C=m1 Thus F4=m1’ (needs an inverter);otherwise: F4=m0+m2+m3+m4+m5+m6+m7
53Exercise F=C(AB+A’B’) Implement the function F using a 2-to-4 decoder and two tri-state buffersF=C(AB+A’B’)
54Exercise - solution F=C(AB+A’B’) = ABC + A’B’C Implement the function F using a 2-to-4 decoder and two tri-state buffersF=C(AB+A’B’) = ABC + A’B’CAF1BC23B’CBC
55Exercise F=C(AB+A’B’) Can you also implement F using a 2-to-4 decoder with enable input and an OR gate?F=C(AB+A’B’)
56Exercise - solution F=C(AB+A’B’) = ABC + A’B’C 1. Using a 2-to-4 decoder with enable input and an OR gate:F=C(AB+A’B’) = ABC + A’B’CENA’B’ABAB1231FENC
57Exercise F=C(AB+A’B’) Can you also implement F using a 2-to-4 decoder with enable input and an NOR gate?F=C(AB+A’B’)
58Exercise - solution F=C(AB+A’B’)=C.(AB) F=C(AB’+A’B)=C .(AB) 1. Using a 2-to-4 decoder with enable input and a NOR gate:F=C(AB+A’B’)=C.(AB)xnorF=C(AB’+A’B)=C .(AB)xorENAB1231A’BAB’FENC
593-8 Encoding m elements n-bit binary code encoding decoding n bits A0 :An-1D0D1Dm-1encodern outputbitsm-elements≤ 2nencodingdecodingA0:An-1D0D1Dm-12-to-4decodern bitsm-elements≤ 2n
60EncodingTypically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears: ex. D1=1 output 0001Examples: Octal-to-Binary encoderOther examples?A0:An-1D0D1Dm-1encoder123m-1n-111Examples: Hex-to-Binary encoderDecimal to BCD encoderDecimal to binary encoderASCI to binaryGrades (ABCDF) to binary: A, B, C, D, F to 3 bit binary code
61Example: A decimal-to-BCD encoder 9876321123456897D9D8D7D0A decimal-to-BCD encoderInputs: 10 bits corresponding to decimal digits 0 through 9, (D0, …, D9)Outputs: 4 bits with BCD codesFunction: If input bit Di is a 1, then the output (A3, A2, A1, A0) is the BCD code for i,
62Truth table of the decimal-to-BCD encoder D9 D8 D7 D6 D5 D4 D3 D2 D1 D0A3 A2 A1 A0Note is no button is pushed: the output will also be 0000! Ths would be the same as if D0 was pushed. One can add a valid signal V that is 1 if a button is pushed and 0 if none is pushed: add an actra row with all inputs and V=0V=D0+D1+D2+…D9What happens when two buttons are pushed? E.g. D1 and D2 together: From the expression one notices that now A0=A1=1 and A2=A3=0 (0011) which is the same as if D3 were pushed!A3 = D8 + D9A2 = D4 + D5 + D6 + D7A1 = D2 + D3 + D6 + D7A0 = D1 + D3 + D5 + D7 + D9From table:We made use of the fact that only one input can be “1” at one time
63Priority EncoderIf more than one input value is 1, then the encoder just designed does not work.An encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.D0D1D2D3A1A0?V123processorTo
64Priority Encoder Example Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority is given to most significant 1 present - Code outputs A2, A1, A0 and V where V indicates at least one 1 present.No. of Min-terms/RowInputsOutputsD4D3D2D1D0A2A1A0V124816X X X1X1X XGo over table explaining how entries were obtained, particularly those containing XsX X X1 X X X X
65Priority Encoder Example (continued) One can use a K-map to get equations, but can be read directly from table and manually optimized if careful:A2 = D4A1 = D D2D4D3= F1, F1 = (D3 + D2)D4A0 =V =
66Priority Encoder Example (continued) Could use a K-map to get equations, but can be read directly from table and manually optimized if careful:A2 = D4A1 = D D2D4D3= F1, F1 = (D3 + D2)D4A0 = D D1 = (D D1)D4D3D2V = D4 + F1 + D1 + D0
67Exercise: design a 4 input priority encoder with active low inputs Table:D0D1D2D31231A1A0D3 D2 D1 D0 A1 A0 V?x x 0Vxx x0 x x xTable:D3 D2 D1 D0 A1 A0 V0 x x x0 x xxx x 0Expressions:A1 = D3.D2’ + D3’ = D2’ + D3’A0 = D3D2D1’ + D3’ = D2.D1’ + D3’V = (D3.D2.D1.D0)’
683-9 Selecting (multiplexers) Selecting of data or information is a critical function in digital systems and computersCircuits that perform selecting have:A set of n information inputs from which the selection is madeA set of k control (select) lines for making the selectionA single output123:n-1I0I1I2I3In-1OUTn ≤ 2k inputskSk-1..S1 S0k select lines
69Multiplexer equivalent 1231 0I0I1I2I3OutS1 S0(Ref.: F. Vahid, “Digital Design”, J. Wiley, 2007)
70Many uses of multiplexers In computers to select among signalsTo implement command:Trip controller in a car to display mileage, time, speed, etc.1XYAZif A=0 then Z=XYelse Z=XY(F. Vahid)clockodometerspeedmileage4:11231 0S1 S0Push buttonDisplay
71Example of a 4-input MUX 4 inputs mux requires 2 select lines: 4:1 I0 1231 0I0I1I2I3OutS1 S0I0I1I2I3123OutS1 S0Table (condensed truth table):S1 S0 OUTI0I1I2I3
724:1 MUX realization Expression for OUT Circuit implementation: SOP 4 AND gates (4 product terms)2-to-4 line decoder (to generate the minterms)S1 S0 OUTI0I1I2I3OUT = S1S0 I0+ S1S0 I1+ S1S0 I2+ S1S0 I3m3m2m1m0or OUT = Σ mi Iii=02k-1
744:1 Quad MultiplexerQuad refers to the fact that each input consists of a 4-bit wide signal (vector)I0[3:0]I1[3:0]I2[3:0]I3[3:0]44:11234Out [3:0]1 0S1 S0Single inputs for the select signals
75Exercise Build a 8:1 MUX using two 4:1 and one 2:1 muxes I0 I1 4:1 I2 1231 01OUTS1 S0I4I5I6I74:1123We need 3 select signals: S2,S1 and S0S21 0Ex: S2S1S0=110 : select I6
76ExerciseA student was working late and get confused. He designed the following 8-to-1 MUX but did not label the inputs. Can you do so?S2S1S0out000010S1 S2100110001We need 3 select signals: S2,S1 and S0S2 should be connected to the 2-1 Mux, and S1 to the select “1” input of both 4-1 Muxes; and S0 to the select “0” input.011101111Next, rewire the circuit so that we have a regular 8-1 MUX whose inputs corresponds to the selection code A2A1A0
77ExerciseA student was working late and get confused. He designed the following 8-to-1 MUX but did not label the inputs. Can you do so?S2S1S0240002461357Accesses I06010Accesses I2Top 4-1 muxS1 S21001Accesses I13110Accesses I357001Accesses I0We need 3 select signals: S2,S1 and S0S2 should be connected to the 2-1 Mux, and S1 to the select “1” input of both 4-1 Muxes; and S0 to the select “0” input.011Accesses I1101Accesses I2Bottom 4-1 mux111Accesses I3Next, rewire the circuit so that we have a regular 8-1 MUX whose inputs corresponds to the selection code A2A1A0
78Multiplexer-based combinational circuits realization- Approach 1 A mux can be easily used to implement a function defined by a truth table (lookup table)Indeed the output F of a mux is equal to:F = Σ mi Iii=02k-1ExampleA B OUT =FIIIIm0m1m2m3F= Σm(1,2)Give the input Ii thevalue of 0 or 1as shown in the truth table14:11231 0FA B
79Example: Gray to Binary Code Design a circuit to convert a 3-bit Gray code to a binary codeThe formulation gives the truth table on the rightIt is obvious from this table that X = C and the Y and Z are more complexGrayA B CBinaryx y z1 00 110 1 01 0 1
80Gray to Binary (continued) Rearrange the table so that the input combinations are in counting orderFunctions y and z can be implemented using a dual 8-to-1-line multiplexer by:connecting A, B, and C to the multiplexer select inputsplacing y and z on the two multiplexer outputsconnecting their respective truth table values to the inputs
81Gray to Binary (continued) Note that the multiplexer with fixed inputs is identical to a ROM with 3-bit addresses and 2-bit data!1D04D05D06D07S1S0S2D03D02D01D00OutY8-to-1MUXD14D15D16D17S1S0S2D13D12D11D10OutZ8-to-1MUX1ABCABC
82Multiplexer-based combinational circuits - Approach 2 One can further simplify the implementation:Previous example:ExampleA B OUT FIIIIB1FBA
83Combinational Logic Implementation - Multiplexer Approach 2 Implement any m functions of n + 1 variables by using:An m-wide 2n-to-1-line multiplexerDesign:Find the truth table for the functions.Based on the values of the first n variables, separate the truth table rows into pairsFor each pair and output, define a rudimentary function of the final variable (0, 1, X, )X
84Gray to Binary - Approach 2 Rearranged the table so that the input combinations are in counting order.GrayA B CBinaryx y zRudimentaryFunctions of C for yRudimentary Functions of C for z0 0 00 0 11 1 10 1 00 1 11 0 01 0 11 1 0F = CF = CF = CF = CF = CF = CF = CF = C
85Gray to Binary (continued) Assign the variables and functions to the multiplexer inputs:Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.S1S0D03D02D01D00OutY8-to-1MUXCD13D12D11D10OutZ8-to-1MUXS1S0CCABAB
86Exercise 1 (cont)Implement the function F(A,B,C)=Σm(0,1,2,5) using a 4:1 muxA B C F1C4:11231 0F1CA B
87Exercise: Controller for rear lights of a car Word description of the problem: Design a circuit that controls the rear lights of a car: Left and Right rear lights.Assume that is a single lamp in each of the rear lights.
88Example (continued): Specification The inputs to the controller are:Outputs signals:Name DescriptionLT Left turn signal: causes blinking of left side lightRT Right turn signalEM Emergency flasher: both lights blinkBR Break is applied: both lights are onBL Internal signal of 1Hz frequencyName DescriptionLeft Power control for the left rear lightRight Power control for the right rear light
89Example (continued): Specification 2 The break BR overrides the emergency EM signalThe Left turn LR and Right turn RT overrides the break signals BR.Implement the two power control signals as:Minimized SOPDecoder with NOR gatesMultiplexer
90Example (cont): Formulation LeftLightLT BR EM BL LeftRT BR EM BL Right1RightLight1