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1 Using emulation for RTL performance verification June 4, 2014 DaeSeo Cha Infrastructure Design Center System LSI Division Samsung Electronics Co., Ltd.

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Presentation on theme: "1 Using emulation for RTL performance verification June 4, 2014 DaeSeo Cha Infrastructure Design Center System LSI Division Samsung Electronics Co., Ltd."— Presentation transcript:

1 1 Using emulation for RTL performance verification June 4, 2014 DaeSeo Cha Infrastructure Design Center System LSI Division Samsung Electronics Co., Ltd.

2 2 2/13 Current Performance Verification System Architecture Specification System Requirement RTL Integration FPGA Architectural Performance Exploration SystemC model, real workload aware performance analysis Architectural Performance Verification System C model  Inaccuracy Post-Silicon RTL Performance Verification Sub-system only  Capacity RTL Performance Verification Full chip  Too late in development stage RTL Performance Verification Subsystems/full chip using logic simulation  Slow

3 3 3/13 New Approach for Performance Verification System Architecture Specification System Requirement RTL Integration FPGA Post-Silicon UVM Testebench log GUI Analysis Environment (PRISM) GUI Analysis Environment (PRISM) Accurate Cycle Accuracy Fast 100X+ Early Stage RTL freeze Big capacity Full chip Fast Analysis Correlation/Compare Summary * PRISM: Samsung In-house Tool Fast and Accurate Performance Verification

4 4 4/13  Environment Reuse existing UVM simulation environment without any modification Add PV(Performance Verification) components  PV components Monitor: Collect various performance metrics Traffic Generator: Random or replay RTL IP’s traffic Performance Verification Platform

5 5 5/13 UVM Co-emulation Environment  UVM Architecture for Co-emulation Simulation environment Simulation environment -Incremental elaboration having primary, incremental snapshot -Building test scenarios by combining testbench and design in full-chip Emulation environment Emulation environment -DUT runs in emulator, incremental elaboration scheme used in emulator prim_top sw_top Interface Sequence Test scenario Module Virtual sequencer REG2BUS adapter Register predictor Register Model AXI bus Bus UVC Interface Interrupt hw_top tb_top UVM testbench Simulator DUT Emulator DUT Incr_top

6 6 6/13 Performance Monitor -1/2  Performance Metrics Latency: Min/Max/Average, time-varying, accumulated, distributed Bandwidth: Min/Max/Average, time-varying, accumulated, distributed Utilization: Min/Max/Average, time-varying, accumulated, distributed Address pattern Response time Customized metrics like IP’s internal signals (FIFO level)  Implementation Synthesizable code for both simulation and emulation Collect performance metrics on AXI interface  Issue Run-time overhead in emulation  Synchronization overhead between emulator and simulator Log file PRISM PM PM: performance monitor

7 7 7/13 Performance Monitor – 2/2  Experiments PV results should be recorded in-order Many experiments are done to reduce run-time overhead  GFIFO Transactions are collected in order, it is congruent with the SW simulation Parallel execution of monitor transaction in SW  Improve performance bit a; bit [5:0] b; int c; function void my_mon(bit x1, bit [5:0] x2, int x3); $fdisplay(“%d %d %d”, x1, x2, x3); endfunction; initial $ixc_ctrl("gfifo", “my_mon"); begin my_mon(a, b, c) end bit a; bit [5:0] b; int c; begin $fdisplay (“ %d %d %d”, a, b, c); end MethodDescriptiontbcall syncOverhead No PV MonitorBaseline398- $displaySync with TB using $fdisplay()32,79881X GFIFOBuffering monitored transaction Collecting process in back ground X Simulation Monitor GFIFO

8 8 8/13 Performance Analysis Environment  PRISM (Performance Visualization System) Charting PV results in GUI Easy to find a performance issue by viewing PV results in a single GUI

9 9 9/13 Experimental Result  Application Multimedia test scenarios such as video playback, camera recording  Run-time speed +100x faster than simulation  Bugs found Critical bugs and design weak points which would not been detected during simulation-based verification

10 10 10/13 Conclusion  PV using emulator is a mainstream solution Very fast bring up using UVM Co-emulation Reusing UVM full-chip testbench without any modification PV in early design development stage with cycle accuracy +100x faster speed compared with simulation approach Efficient PV analysis by PRISM  Future Work Add more features to PRISM - correlation, smart PV report etc. Develop ACE PV Monitor for dealing with cache-coherency Deploy UVM Co-emulation for other test scenarios

11 11 11/13 Thank you


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