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線性穩壓器 (2) Linear Regulators (2) Instructor: Po-Yu Kuo ( 郭柏佑 ) 國立雲林科技大學 電子工程系.

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Presentation on theme: "線性穩壓器 (2) Linear Regulators (2) Instructor: Po-Yu Kuo ( 郭柏佑 ) 國立雲林科技大學 電子工程系."— Presentation transcript:

1 線性穩壓器 (2) Linear Regulators (2) Instructor: Po-Yu Kuo ( 郭柏佑 ) 國立雲林科技大學 電子工程系

2 A typical series regulator which consists of four main building blocks: Structure of LDO 2

3 Voltage Reference (V ref ): a very stable voltage with respect to temperature change and input voltage variations, usually of the bandgap type. Error Amplifier (A(s)): a very high (dc) gain opamp to achieve a close to zero error signal V err =V + - V -. Feedback Network: R1 and R2 define the feedback factor and generate V fb to be compared with Vref to get the designed output voltage Vo. Series Pass/Power Transistor (Q1): power transistor configuration to pass high current from the source to output. As it handles large current, the size of pass transistor dominates the area of the whole series regulator. Structure of LDO 3

4 Dropout Voltage (Vdo) is the minimum voltage difference between the input and output under which the regulator still able to maintain the output within the specification. With a Li-Ion battery as Vin, Vin varies from 2.7V to 4.2V. V do,max =4.2-V ov,ML Structure of LDO 4

5 5

6 Two Categories: Regulating (accuracy) performance Line regulation, load regulation, temperature dependence, transient overshoot, transient recovery time, stability Power Characteristics I o, Quiescent current I q, V in & V o ( ) Specifications of LDO 6

7 Current Efficiency : where I q is the quiescent current of LDO In LDO design for portable applications, I o is usually much larger than I q with > 99% efficiency When I o is 0, I q should be minimized (I 3 should be small by large values of R 1 and R 2 ) Efficiency 7

8 Smaller dropout voltage causes a higher power conversion efficiency especially Io >> Iq In light-load condition (small Io), the efficiency is poorer as I 1, I 2, and I 3 are close to I o Efficiency 8

9 V SD must be always larger than V ov at different conditions Design at the worst case: largest V ov at I o(max) and μ p(min) at the maximum temperature By using minimum L (the smallest transistor and hence parasitic capacitance), keep increasing W until meeting the dropout specification IR at the routing metals increase V DO Design margin by experience-generally the chosen W is times of the theoretical W Dropout Voltage and Power-Transistor Sizing 9

10 Load Regulation (R): closed-loop output resistance of LDO R o is the open-loop output resistance of the pass transistor as R f1, R f2 >> R o Better load regulation is achieved by smaller R o (using minimum channel length of the pass transistor) and larger loop-gain magnitude As R o 1/I o, high Io range gives better load regulation Load Regulation 10

11 g mp is the transconductance of power PMOS transistor Line regulation is independent of the gain of the power transistor Line regulation can be improved by a high-gain error amplifier Other error sources on line regulation are voltage reference and offset voltage of the error amplifier Line Regulation 11

12 G m and R o can be found individually Input-Output voltage gain can be found by the product of G m and R o Review on Voltage Gain 12

13 Voltage gain of the error amplifier is not the only parameter to improve line regulation Good designs on supply independence of V ref and reducing systematic offset of error amplifier are very important Line Regulation Including Other Errors 13

14 Variation of Vo at different temperature depends on both voltage reference and error amplifier design R f1 and R f2 must be made by the same material and closely placed Temperature Coefficient 14

15 Load Transient Response 15

16 Better load transient response by t resp ↓, C o ↑, R e ↓ and L c ↓. Load Transient Response 16

17 AC Design (1): Loop-Gain Analysis 17

18 AC Design (2): Loop-Gain Analysis 18

19 AC Design (3): Loop-Gain Analysis 19

20 AC Design (4): Loop-Gain Analysis 20 z e should cancel p2 within one decade of frequency for stability Parasitic pole(s), ppar, must be far away from the unity-gain frequency (UGF) Different UGFs are resulted from different Re values such as z e locating before or after p 2 p 2 locates at very low frequency as C pa and r a are large Required large C o and R e Large C o is unfavorable in the cost consideration Low-frequency pole-zero cancellation is unfavorable to load transient recovery time

21 LDO with Voltage Buffer 21 Smaller required R e can be achieved by inserting a low output-resistance (1/g mb ) voltage buffer One more pole (p 3 ) is created but is located at high frequency due to small output resistance of the voltage buffer p 2 (with voltage buffer) locates at a higher frequency than the one without voltage buffer (C b << C g )

22 Effect of Load Currents on Stability 22 Loop gain is larger when I o is smaller due to g mp r o 1/ √I o p 1 is lower when I o is smaller due to larger r o of the power transistor (r o 1/I o ) Worst-case stability at maximum I o Compensation at max. I o

23 Effect of Loop-Gain Magnitude on Stability 23 Larger loop gain by increasing r a of the error amplifier p 2 → p 2 ’ A larger Re is needed to create a zero at lower frequency (z e → z e ’) Larger loop gain → more unstable as p 3 may be below the UGF of loop gain A larger C o is generally needed

24 Loop Gain Simulation 24

25 Summary of LDO Specifications 25

26 Circuit Implementations 26 Circuit of LDO consists of R 1 and R 2 C in and C o V ref Error Amplifier Voltage Buffer Power Transistor V in,min = V ov,Me1 + V gs,Mb2 + V gs,Mp Low-voltage operation impossible!

27 Circuit Implementations 27 BJT has a small V BE drop (~0.7V) The circuit can operate at lower input supply compared to the previous case Smaller input capacitance for small V BE Base current introduces larger offset voltage and hence degrades accuracy of the output voltage

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