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We have so far seen the structure of a differential amplifier, the input stage of an operational amplifier. The second stage of the simplest possible operational.

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Presentation on theme: "We have so far seen the structure of a differential amplifier, the input stage of an operational amplifier. The second stage of the simplest possible operational."— Presentation transcript:

1 We have so far seen the structure of a differential amplifier, the input stage of an operational amplifier. The second stage of the simplest possible operational amplifier could be 1. Class A amplifier. 2. Source follower. 3. Push-Pull amplifier ( inverting and follower). 4. Bipolar Output

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7 Let us now get back to the factors characterizing an operational amplifiers. Gain; Gain Bandwidth product; CMRR; PSRR; CMR; Output Swing; Input Offset; Noise Settling Time; Slew Rate;.

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9 Power Supply Rejection ratio (PSRR) This gives a measure of noise introduced at the output due to fluctuations in the power supply.

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11 Frequency Response: Assuming that all the inter electrode capacitances are negligibly small it is evident to see that the operational amplifier structure will have three poles contributed by the capacitances C M, C 1 and C L. Predominantly the poles will be due to C 1 and C L

12 In all operational amplifier application they are used in a feedback mode. For the stability of the amplifier configuration we desire that the loop gain be less than unity when the phase shift nears 180º (normally) at 135º.

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14 Depending on the relative values of  1 and  2 will determine whether the loop gain will reach unity before the phase shift reaches 0º. The closer the two frequencies  1 and  2 the less stable will the circuit be. We define two quantities here namely Gain Margin and Phase Margin. Gain margin is the loop gain when the phase is 0º and Phase Margin is the difference from 0º, then phase when the loop gain is unity.

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19 The requirement that phase margin should be atleast 60º means that This gives us far large gain, |p 2 |  2.2 GB. Demanding z 1 >> p 1 gives along with p 2 |  2.2 GB

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22 To remove the zero and have the second pole still farther away, we do pole zero cancellation i.e put z 1 = p 2. This gives

23 Power Supply Rejection Ratio (PSRR):

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34 g m1 = g m2 = g m1, (g ds2 + g ds3 ) -1 = R 1, and (g ds6 + g ds7 ) -1 = R 2 Slew rate = C C /I 5 ; Settling time: 5(V DD - V SS )/I 5

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37 Gain at mid frequency > 5000; Gain Bandwidth Product: 5MHz; Input Common Mode Range: -1 to 2V; Load Capacitance: 10pF; Slew Rate: 10V/  s; Output Voltage Swing: ± 2V and Power Dissipation:  2mW

38 To start with we choose an appropriate value of C c. Assuming a phase margin of > 60º choose C c = 3pF. Given a slew rate of 10V/  s we have

39 Pole due to mirror capacitance  g m3 /(2C gs3 ) where C gs = 0.67 W 3 L 3 C ox. Assuming a channel length of 1  m we get |p 3 |  448 MHz >> GB. Using the expression for GB we have g m1 = GB x C c = (5 x 10 6) 2  (3 x ) =  S

40 We have from V DS5 To obtain W/L ratio for M 6 we take g m6 = 10 g m1 = Since we know (W/L) 3 = 15 and I 3 = 15  A we have g m3 = 150. Hence we have From the expression for V G1 min

41 From the expression for g m we obtain I 6 as Using the values of (W/L) 6 = 94 and (W/L) 7 = 14 we get V DS7 (sat) = 0.351V and V DS6 (sat) =0.201V

42 The total Power Dissipation is given by The over all gain is given by


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