Presentation on theme: "DAP teaching computer architecture at Berkeley since 1977"— Presentation transcript:
1Computer Architecture: A Constructive Approach Introduction to SMIPS Jihong Kim DAPteaching computer architecture at Berkeley since 1977Co-athor of textbook used in classBest known for being one of pioneers of RISCcurrently author of article on future of microprocessors in SciAm Sept 1995RYtook 152 as student, TAed 152,instructor in 152undergrad and grad work at Berkeleyjoined NextGen to design fact 80x86 microprocessorsone of architects of UltraSPARC fastest SPARC mper shipping this Fall
2Stored Program Concept Instructions are bits (i.e., as numbers)Programs are stored in memoryto be read or written just like dataFetch & Execute CycleInstructions are fetched and put into a special registerBits in the register "control" the subsequent actionsFetch the next instruction and continueTreating Instructions in thesame way as Datamemory for data, programs,compilers, editors, etc.
3Multiple Levels of Representation temp = v[k];v[k] = v[k+1];v[k+1] = temp;High Level Language ProgramCompilerlw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)Assembly Language ProgramAssemblerMachine Language ProgramMachine InterpretationControl Signal SpecificationALUOP[0:3] <= InstReg[9:11] & MASKHigh and low signals on control lines
4Instruction Set Architecture (subset of Computer Arch.) “ ... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior,as distinct from the organization of the data flows and controls, the logical design, and the physical implementation. “ Amdahl, Blaaw, and Brooks, 1964SOFTWARE
6MIPS I Instruction Set Architecture r0 - r31PCHILORegistersInstruction CategoriesLoad/StoreComputationalJump and BranchFloating PointcoprocessorMemory ManagementSpecialOPrsrtrdsafunctimmediatejump target3 Instruction Formats: all 32 bits wideSMIPS: a subset of the full MIPS32 ISA
7Execution Cycle (Conceptual Programmer’s View) InstructionFetchDecodeOperandExecuteResultStoreNextObtain instruction from program storageDetermine required actions and instruction sizeLocate and obtain operand dataCompute result value or statusDeposit results in storage for later useDetermine successor instruction
8MIPS Registers: Fast Locations for Data 32 32-bit registers: $0, $1, … , $31operands for integer arithmeticaddress calculationstemporary locationsspecial-purpose functions defined by convention1 32-bit Program Counter (PC)2 32-bit registers HI & LO:used for multiply & divide32 32-bit registers: $f0, … $f31floating-point arithmetic (often used as bit registers)
9MIPS Load-Store Architecture Every operand must be in a register (a few exceptions)Variables have to be loaded in registers.Results have to be stored in memory.load b in register Rxload c in register RyRz = Rx + Rystore Rz in aRt = Rz + Rxstore Rt in da = b + cd = a + bmore variables than registers, so need explicit load and stores.
10All instructions have 3 operands MIPS arithmeticAll instructions have 3 operandsOperand order is fixed (destination first) Example:C code: A = B + CMIPS code: add $s0, $s1, $s2C code: A = B + C + D; E = F - A;MIPS code: add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0
11Compiler associates variables with registers Registers vs. MemoryArithmetic instruction’s operands must be registers: only 32 registers providedCompiler associates variables with registersWhat about programs with lots of variables?Spilling registersFor high performance, use registers efficiently!ProcessorI/OControlDatapathMemoryInputOutput
12Viewed as a large, single-dimension array, with an address. Memory OrganizationViewed as a large, single-dimension array, with an address.A memory address is an index into the array"Byte addressing" means that the index points to a byte of memory.123456...8 bits of dataQ: How to specify a memory location?
13Load & Store Instructions Base+Offset addressing mode: offset(base register)e.g., 32($s3)Example:C code: A = h + A;A: an array of 100 wordsthe base address of the array A is in $s3MIPS code:lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3)Store word has destination lastbase register: $s3offset: 32
14Example: Compiling using a Variable Array Index C code: g = h + A[i]$s3: base register for Ag, h, i: $s1, $s2, $s4MIPS code:add $t1, $s4, $s # $t1 = 2 * iadd $t1, $t1, $t # $t1 = 4 * iadd $t1, $t1, $s # $t1 = address of A[i]lw $t0, 0($t1) # $t0 = A[i]add $s1, $s2, $t # g = h + A[i]
15Decision making instructions Control: bne & beqDecision making instructionsalter the control flow,i.e., change the "next" instruction to be executedMIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, LabelExample: if (i==j) h = i + j;bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....
16More Branch Instructions blez s, labelif (s <= 0) goto labelbnez s, labelif (s != 0) goto label